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IS61SP12836-200B PDF预览

IS61SP12836-200B

更新时间： 2024-11-20 07:39:19
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
15页 124K
描述
Cache SRAM, 128KX36, 3.1ns, CMOS, PBGA119, PLASTIC, BGA-119

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IS61SP12836-200B 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：PLASTIC, BGA-119针数：119
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.86
最长访问时间：3.1 nsJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：4718592 bit内存集成电路类型：CACHE SRAM
内存宽度：36功能数量：1
端子数量：119字数：131072 words
字数代码：128000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：128KX36封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：240认证状态：Not Qualified
座面最大高度：2.41 mm最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：14 mm

IS61SP12836-200B 数据手册

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®
IS61SP12832  
IS61SP12836  
128K x 32, 128K x 36 SYNCHRONOUS  
PIPELINED STATIC RAM  
ISSI  
APRIL 2001  
FEATURES  
DESCRIPTION  
The ISSI IS61SP12832 and IS61SP12836 is a high-speed  
synchronous static RAM designed to provide a burstable,  
high-performance memory for high speed networking and  
communication applications. It is organized as 131,072  
words by 32 bits and 36 bits, fabricated with ISSI's ad-  
vanced CMOS technology. The device integrates a 2-bit  
burst counter, high-speed SRAM core, and high-drive  
capability outputs into a single monolithic circuit. All syn-  
chronous inputs pass through registers controlled by a  
positive-edge-triggered single clock input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Pentium™ or linear burst sequence control using  
MODE input  
• Three chip enables for simple depth expansion  
and address pipelining  
• Common data inputs and data outputs  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock input. Write cycles can be from  
one to four bytes wide as controlled by the write control  
inputs.  
• JEDEC 100-Pin TQFP and  
119-pin PBGA package  
• Single +3.3V, +10%, –5% power supply  
• Power-down snooze mode  
Separate byte enables allow individual bytes to be written.  
BW1 controls DQa, BW2 controls DQb, BW3 controls  
DQc, BW4 controls DQd, conditioned by BWE being  
LOW. A LOW on GW input would cause all bytes to be  
written.  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally and controlled by the ADV (burst address  
advance) input pin.  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW.  
Interleave burst is achieved when this pin is tied HIGH or  
left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-200  
3.1  
5
-166  
3.5  
6
-150  
3.8  
-133  
4
-5  
5
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
6.7  
7.5  
133  
10  
100  
ns  
Frequency  
200  
166  
150  
MHz  
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any  
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
1
04/17/01  
1234567...15

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IS61SP12836-3.5TQ ETC

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IS61SP12836-3.8TQ ETC

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IS61SP12836-3.8TQI ETC

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 		x36 Fast Synchronous SRAM
IS61SP12836-5B ICSI

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 		128K x 36 SYNCHRONOUS PIPELINED STATIC RAM
IS61SP12836-5TQ ICSI

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 		128K x 36 SYNCHRONOUS PIPELINED STATIC RAM
IS61SP12836-5TQ ISSI

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 		Cache SRAM, 128KX36, 5ns, CMOS, PQFP100, TQFP-100
IS61SP12836-5TQI ISSI

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 		Cache SRAM, 128KX36, 5ns, CMOS, PQFP100, TQFP-100

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