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IS61NP25618-133B2 PDF预览

IS61NP25618-133B2

更新时间： 2024-11-11 14:42:55
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
21页 129K
描述
ZBT SRAM, 256KX18, 4.2ns, CMOS, PBGA119, PLASTIC, BGA-119

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IS61NP25618-133B2 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：PLASTIC, BGA-119针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.92
最长访问时间：4.2 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：133 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B119JESD-609代码：e0
长度：22 mm内存密度：4718592 bit
内存集成电路类型：ZBT SRAM内存宽度：18
功能数量：1端子数量：119
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256KX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：240
电源：3.3 V认证状态：Not Qualified
座面最大高度：2.41 mm最大待机电流：0.01 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.29 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

IS61NP25618-133B2 数据手册

 浏览型号IS61NP25618-133B2的Datasheet PDF文件第2页浏览型号IS61NP25618-133B2的Datasheet PDF文件第3页浏览型号IS61NP25618-133B2的Datasheet PDF文件第4页浏览型号IS61NP25618-133B2的Datasheet PDF文件第5页浏览型号IS61NP25618-133B2的Datasheet PDF文件第6页浏览型号IS61NP25618-133B2的Datasheet PDF文件第7页 
®
IS61NP12832 IS61NP12836 IS61NP25618  
IS61NLP12832 IS61NLP12836 IS61NLP25618 ISSI  
128K x 32, 128K x 36 and 256K x 18  
PIPELINE 'NO WAIT' STATE BUS SRAM  
NOVEMBER 2002  
FEATURES  
DESCRIPTION  
The 4 Meg 'NP' product family feature high-speed,  
low-power synchronous static RAMs designed to provide  
a burstable, high-performance, 'no wait' state, device for  
network and communications customers. They are  
organized as 131,072 words by 32 bits, 131,072 words  
by 36 bits and 262,144 words by 18 bits, fabricated with  
ISSI's advanced CMOS technology.  
• 100 percent bus utilization  
• No wait cycles between Read and Write  
• Internal self-timed write cycle  
• Individual Byte Write Control  
• Single R/W (Read/Write) control pin  
• Clock controlled, registered address,  
data and control  
Incorporating a 'no wait' state feature, wait cycles are  
eliminated when the bus switches from read to write, or  
write to read. This device integrates a 2-bit burst counter,  
high-speed SRAM core, and high-drive capability outputs  
into a single monolithic circuit.  
• Interleaved or linear burst sequence control  
using MODE input  
• Three chip enables for simple depth expansion  
and address pipelining for TQFP  
Allsynchronousinputspassthroughregistersarecontrolled  
byapositive-edge-triggeredsingleclockinput.Operations  
may be suspended and all synchronous inputs ignored  
when Clock Enable, CKE is HIGH. In this state the internal  
device will hold their previous values.  
• Power Down mode  
• Common data inputs and data outputs  
• CKE pin to enable clock and suspend operation  
• JEDEC 100-pin TQFP and 119 PBGA packages  
• Single +3.3V power supply (± 5%)  
• NP Version: 3.3V I/O Supply Voltage  
• NLP Version: 2.5V I/O Supply Voltage  
• Industrialtemperatureavailable  
All Read, Write and Deselect cycles are initiated by the  
ADV input. When the ADV is HIGH the internal burst  
counter is incremented. New external addresses can be  
loaded when ADV is LOW.  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock inputs and when WE is LOW.  
Separate byte enables allow individual bytes to be written.  
A burst mode pin (MODE) defines the order of the burst  
sequence.WhentiedHIGH,theinterleavedburstsequence  
is selected. When tied LOW, the linear burst sequence is  
selected.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-150  
3.8  
-133  
4.2  
-100  
5
Units  
ns  
Clock Access Time  
CycleTime  
tKC  
6.7  
7.5  
10  
ns  
Frequency  
150  
133  
100  
MHz  
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
Rev. B  
1
11/21/02  
1234567...21

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与IS61NP25618-133B2相关器件

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IS61NP25618-133TQ ISSI

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IS61NP25618-133TQI ISSI

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 		ZBT SRAM, 256KX18, 4.2ns, CMOS, PQFP100, TQFP-100
IS61NP25618-150B ISSI

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 		PIPELINE NO WAIT STATE BUS SRAM
IS61NP25618-150B2 ISSI

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 		ZBT SRAM, 256KX18, 3.8ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61NP25618-150TQ ISSI

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 		PIPELINE NO WAIT STATE BUS SRAM
IS61NP25618-5B ISSI

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 		PIPELINE NO WAIT STATE BUS SRAM
IS61NP25618-5TQ ISSI

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 		PIPELINE NO WAIT STATE BUS SRAM
IS61NP25632 ISSI

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 		256K x 32, 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM
IS61NP25632-100BI ISSI

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 		ZBT SRAM, 256KX32, 5ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61NP25632-10TQI ISSI

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 		ZBT SRAM, 256KX32, 5ns, CMOS, PQFP100, TQFP-100

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