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IS61NLP12836B-250TQ

更新时间： 2024-11-18 05:39:35

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
29页	445K
描述
128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM

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IS61NLP12832B

IS61NLP12836B/IS61NVP12836B

IS61NLP25618A/IS61NVP25618A

128K x 32, 128K x 36, and 256K x 18

4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

SEPTEMBER 2007

FEATURES

DESCRIPTION

Theꢀ4ꢀMegꢀ'NLP/NVP'ꢀproductꢀfamilyꢀfeatureꢀhigh-speed,ꢀ

low-powerꢀsynchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀ

aꢀburstable,ꢀhigh-performance,ꢀ'noꢀwait'ꢀstate,ꢀdeviceꢀforꢀ

networkingꢀandꢀcommunicationsꢀapplications.ꢀTheyꢀareꢀ

organizedꢀasꢀ128Kꢀwordsꢀbyꢀ32ꢀbits,ꢀ128Kꢀwordsꢀbyꢀ36ꢀ

bits,ꢀandꢀ256Kꢀꢀwordsꢀbyꢀ18ꢀbits,ꢀfabricatedꢀwithꢀISSI'sꢀ

advanced CMOS technology.

•ꢀ 100ꢀpercentꢀbusꢀutilization

•ꢀ NoꢀwaitꢀcyclesꢀbetweenꢀReadꢀandꢀWrite

•ꢀ Internalꢀself-timedꢀwriteꢀcycle

•ꢀ IndividualꢀByteꢀWriteꢀControl

•ꢀ SingleꢀR/Wꢀ(Read/Write)ꢀcontrolꢀpin

•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀꢀ

ꢀ

Incorporatingꢀ aꢀ 'noꢀ wait'ꢀ stateꢀ feature,ꢀ waitꢀ cyclesꢀ areꢀ

eliminated when the bus switches from read to write, or

writeꢀtoꢀread.ꢀThisꢀdeviceꢀintegratesꢀaꢀ2-bitꢀburstꢀcounter,ꢀ

high-speedꢀSRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀ

into a single monolithic circuit.

data and control

•ꢀ Interleavedꢀorꢀlinearꢀburstꢀsequenceꢀcontrolꢀus-

ing MODE input

•ꢀ Threeꢀchipꢀenablesꢀforꢀsimpleꢀdepthꢀexpansionꢀ

Allsynchronousinputspassthroughregistersarecontrolled

byꢀaꢀpositive-edge-triggeredꢀsingleꢀclockꢀinput.ꢀOperationsꢀ

may be suspended and all synchronous inputs ignored

when Clock Enable, CKEꢀisꢀHIGH.ꢀInꢀthisꢀstateꢀtheꢀinternalꢀ

device will hold their previous values.

and address pipelining

•ꢀ PowerꢀDownꢀmode

•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs

•ꢀ CKE pin to enable clock and suspend operation

AllꢀRead,ꢀWriteꢀandꢀDeselectꢀcyclesꢀareꢀinitiatedꢀbyꢀtheꢀADVꢀ

input.ꢀWhenꢀtheꢀADVꢀisꢀHIGHꢀtheꢀinternalꢀburstꢀcounterꢀ

isꢀincremented.ꢀNewꢀexternalꢀaddressesꢀcanꢀbeꢀloadedꢀ

whenꢀADVꢀisꢀLOW.

•ꢀ JEDECꢀ100-pinꢀTQFP,ꢀ165-ballꢀPBGAꢀandꢀ119-

ballꢀPBGAꢀpackages

•ꢀ Powerꢀsupply:

Writeꢀ cyclesꢀ areꢀ internallyꢀ self-timedꢀ andꢀ areꢀ initiatedꢀ

by the rising edge of the clock inputs and when WE is

LOW.ꢀSeparateꢀbyteꢀenablesꢀallowꢀindividualꢀbytesꢀtoꢀbeꢀ

written.

NVP:ꢀV^{d d}2.5Vꢀ(±ꢀ5%),ꢀVd d q ꢀ2.5Vꢀ(±ꢀ5%)

NLP:ꢀV^{d d}ꢀ3.3Vꢀ(±ꢀ5%),ꢀVd d q ꢀ3.3V/2.5Vꢀ(±ꢀ5%)

•ꢀ Industrialꢀtemperatureꢀavailable

•ꢀ Lead-freeꢀavailable

ꢀAꢀburstꢀmodeꢀpinꢀ(MODE)ꢀdeﬁnesꢀtheꢀorderꢀofꢀtheꢀburstꢀ

sequence.ꢀWhenꢀtiedꢀHIGH,ꢀtheꢀinterleavedꢀburstꢀsequenceꢀ

isꢀselected.ꢀWhenꢀtiedꢀLOW,ꢀtheꢀlinearꢀburstꢀsequenceꢀisꢀ

selected.

FAST ACCESS TIME

Symbol

Parameter

-250

2.6ꢀ

4ꢀ

-200

3.1ꢀ

5ꢀ

Units

tk q ꢀ

tk c ꢀ

ꢀ

ClockꢀAccessꢀTimeꢀ

CycleꢀTimeꢀ

ꢀ

Frequencyꢀ

250ꢀ

200ꢀ

MHz

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device speciﬁcation before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com

Rev. D

09/10/07

12 3 4 5 6 7...29

中文翻译

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与IS61NLP12836B-250TQ相关器件

型号	品牌	获取价格	描述	数据表
IS61NLP12836B-250TQI	ISSI	获取价格	128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM
IS61NLP12836EC-200B3	ISSI	获取价格	ZBT SRAM, 128KX36, 3.1ns, CMOS, PBGA165, TFBGA-165
IS61NLP12836EC-200B3LI	ISSI	获取价格	ZBT SRAM, 128KX36, 3.1ns, CMOS, PBGA165, TFBGA-165
IS61NLP12836EC-200B3LI-TR	ISSI	获取价格	IC SRAM 4.5MBIT 200MHZ 165BGA
IS61NLP12836EC-200TQLI	ISSI	获取价格	IC SRAM 4.5M PARALLEL 100LQFP
IS61NLP12836EC-250B3L	ISSI	获取价格	ZBT SRAM, 128KX36, 2.6ns, CMOS, PBGA165, TFBGA-165
IS61NLP204818-166B3I	ISSI	获取价格	ZBT SRAM, 2MX18, 3.5ns, CMOS, PBGA165, PLASTIC, BGA-165
IS61NLP204818-166TQ	ISSI	获取价格	ZBT SRAM, 2MX18, 3.5ns, CMOS, PQFP100, TQFP-100
IS61NLP204818A	ISSI	获取价格	1Mb x 36 and 2Mb x 18 STATE BUS SRAM
IS61NLP204818A-166B3	ISSI	获取价格	1Mb x 36 and 2Mb x 18 STATE BUS SRAM

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