Datasheet > IS61NLP204818A

IS61NLP204818A

更新时间： 2024-11-21 05:39:35

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
22页	223K
描述
1Mb x 36 and 2Mb x 18 STATE BUS SRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IS61NLP204818A 数据手册

IS61NLP102436A/IS61NVP102436A

IS61NLP204818A/IS61NVP204818A

1Mb x 36 and 2Mb x 18

36Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

SEPTEMBER2007

FEATURES

DESCRIPTION

The 36 Meg 'NLP/NVP' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

networking and communications applications. They are

organizedas1Mwordsby36bitsand2M wordsby18bits,

fabricated with ISSI's advanced CMOS technology.

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

• Clock controlled, registered address,

data and control

• Interleaved or linear burst sequence control using

MODE input

Allsynchronousinputspassthroughregistersarecontrolled

byapositive-edge-triggeredsingleclockinput.Operations

may be suspended and all synchronous inputs ignored

when Clock Enable, CKE is HIGH. In this state the internal

device will hold their previous values.

• Three chip enables for simple depth expansion

and address pipelining

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

• JEDEC 100-pin TQFP and 165-ball PBGA

packages

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when WE is LOW.

Separate byte enables allow individual bytes to be written.

• Power supply:

NVP: V^DD2.5V ( 5ꢀ), VDDQ 2.5V ( 5ꢀ)

NLP: V^DD3.3V ( 5ꢀ), VDDQ 3.3V/2.5V ( 5ꢀ)

A burst mode pin (MODE) defines the order of the burst

sequence.WhentiedHIGH,theinterleavedburstsequence

is selected. When tied LOW, the linear burst sequence is

selected.

• Industrial temperature available

• Lead-free available

FAST ACCESS TIME

Symbol

tKQ

Parameter

-200

3.1

-166

3.5

Units

Clock Access Time

CycleTime

tKC

Frequency

200

166

MHz

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany

publishedinformationandbeforeplacingordersforproducts.

Integrated Silicon Solution, Inc.

Rev. A

09/13/07

12 3 4 5 6 7...22

中文翻译

下载PDF

与IS61NLP204818A相关器件

型号	品牌	获取价格	描述	数据表
IS61NLP204818A-166B3	ISSI	获取价格	1Mb x 36 and 2Mb x 18 STATE BUS SRAM
IS61NLP204818A-166B3I	ISSI	获取价格	1Mb x 36 and 2Mb x 18 STATE BUS SRAM
IS61NLP204818A-166TQ	ISSI	获取价格	1Mb x 36 and 2Mb x 18 STATE BUS SRAM
IS61NLP204818A-166TQI	ISSI	获取价格	1Mb x 36 and 2Mb x 18 STATE BUS SRAM
IS61NLP204818A-166TQL	ISSI	获取价格	1Mb x 36 and 2Mb x 18 STATE BUS SRAM
IS61NLP204818A-166TQLI	ISSI	获取价格	1Mb x 36 and 2Mb x 18 STATE BUS SRAM
IS61NLP204818B-200TQL	ISSI	获取价格	ZBT SRAM, 2MX18, 3.1ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-100
IS61NLP204818B-200TQLI	ISSI	获取价格	ZBT SRAM, 2MX18, 3.1ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-100
IS61NLP204818B-250B3L	ISSI	获取价格	ZBT SRAM, 2MX18, 2.6ns, CMOS, PBGA165, 15 X 13 MM, 1 MM PITCH, LEAD FREE, PLASTIC, TFBGA-1
IS61NLP204836B	ISSI	获取价格	100 percent bus utilization

与IS61NLP204818A相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

28
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

21
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

50
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

48

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61NLP204818A

IS61NLP204818A 数据手册

与IS61NLP204818A相关器件

与IS61NLP204818A相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61NLP204818A

IS61NLP204818A 数据手册

与IS61NLP204818A相关器件

与IS61NLP204818A相关文章

您还可以找

您在本页遇到什么问题？