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IS61NLP12836EC-200TQLI PDF预览

IS61NLP12836EC-200TQLI

更新时间： 2024-11-18 22:58:03
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器
页数 文件大小 规格书
40页 2406K
描述
IC SRAM 4.5M PARALLEL 100LQFP

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IS61NLP12836EC-200TQLI 数据手册

 浏览型号IS61NLP12836EC-200TQLI的Datasheet PDF文件第2页浏览型号IS61NLP12836EC-200TQLI的Datasheet PDF文件第3页浏览型号IS61NLP12836EC-200TQLI的Datasheet PDF文件第4页浏览型号IS61NLP12836EC-200TQLI的Datasheet PDF文件第5页浏览型号IS61NLP12836EC-200TQLI的Datasheet PDF文件第6页浏览型号IS61NLP12836EC-200TQLI的Datasheet PDF文件第7页 
IS61(4)NLP12836EC/IS61(4)NVP12836EC/IS61(4)NLP12832EC  
IS61(4)NVP12832EC/IS61(4)NLP25618EC/IS61(4)NVP25618EC  
128K x36/32 and 256K x18 4Mb, ECC, PIPELINE 'NO WAIT' STATE  
BUS SYNCHRONOUS SRAM  
AUGUST 2019  
FEATURES  
DESCRIPTION  
•
•
•
•
•
•
100 percent bus utilization  
The 4Mb product family features high-speed, low-  
power synchronous static RAMs designed to  
provide a burstable, high-performance, 'no wait'  
state, device for networking and communications  
applications. They are organized as 128K words  
by 36 bits and 256K words by 18 bits, fabricated  
with ISSI's advanced CMOS technology.  
Incorporating a 'no wait' state feature, wait cycles  
are eliminated when the bus switches from read  
to write, or write to read. This device integrates a  
2-bit burst counter, high-speed SRAM core, and  
high-drive capability outputs into a single  
monolithic circuit.  
All synchronous inputs pass through registers are  
controlled by a positive-edge-triggered single  
clock input. Operations may be suspended and all  
synchronous inputs ignored when Clock Enable,  
/CKE is HIGH. In this state the internal device will  
hold their previous values.  
All Read, Write and Deselect cycles are initiated  
by the ADV input. When the ADV is HIGH the  
internal burst counter is incremented. New  
external addresses can be loaded when ADV is  
LOW.  
Write cycles are internally self-timed and are  
initiated by the rising edge of the clock inputs and  
when /WE is LOW. Separate byte enables allow  
individual bytes to be written.  
No wait cycles between Read and Write  
Internal self-timed write cycle  
Individual Byte Write Control  
Single R/W (Read/Write) control pin  
Clock controlled, registered address, data and  
control  
•
•
Interleaved or linear burst sequence control  
using MODE input  
Three chip enables for simple depth  
expansion and address pipelining  
Power Down mode  
•
•
•
Common data inputs and data outputs  
/CKE pin to enable clock and suspend  
operation  
•
•
JEDEC 100-pin QFP, 165-ball BGA and 119-  
ball BGA packages  
Power supply:  
NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)  
NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)  
JTAG Boundary Scan for BGA packages  
Industrial and Automotive temperature support  
Lead-free available  
•
•
•
•
A burst mode pin (MODE) defines the order of the  
burst sequence. When tied HIGH, the interleaved  
burst sequence is selected. When tied LOW, the  
linear burst sequence is selected  
Error Detection and Error Correction  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
Clock Access Time  
Cycle time  
250  
2.6  
4
200  
3.1  
5
Units  
ns  
tKC  
ns  
fMAX  
Frequency  
250  
200  
MHz  
Copyright © 2019 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can  
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such  
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. D3  
1
08/12/2019  
1234567...40

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IS61NLP204818-166B3I ISSI

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IS61NLP204818A-166B3 ISSI

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IS61NLP204818A-166B3I ISSI

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 		1Mb x 36 and 2Mb x 18 STATE BUS SRAM
IS61NLP204818A-166TQ ISSI

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 		1Mb x 36 and 2Mb x 18 STATE BUS SRAM
IS61NLP204818A-166TQI ISSI

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 		1Mb x 36 and 2Mb x 18 STATE BUS SRAM
IS61NLP204818A-166TQL ISSI

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 		1Mb x 36 and 2Mb x 18 STATE BUS SRAM
IS61NLP204818A-166TQLI ISSI

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 		1Mb x 36 and 2Mb x 18 STATE BUS SRAM

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