Datasheet > 暂无类别数据> IS61NLP12832B-200B2

IS61NLP12832B-200B2

更新时间： 2024-11-18 05:39:35

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
29页	445K
描述
128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IS61NLP12832B-200B2 数据手册

浏览型号IS61NLP12832B-200B2的Datasheet PDF文件第2页

浏览型号IS61NLP12832B-200B2的Datasheet PDF文件第3页

浏览型号IS61NLP12832B-200B2的Datasheet PDF文件第4页

浏览型号IS61NLP12832B-200B2的Datasheet PDF文件第5页

浏览型号IS61NLP12832B-200B2的Datasheet PDF文件第6页

IS61NLP12832B

IS61NLP12836B/IS61NVP12836B

IS61NLP25618A/IS61NVP25618A

128K x 32, 128K x 36, and 256K x 18

4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

SEPTEMBER 2007

FEATURES

DESCRIPTION

Theꢀ4ꢀMegꢀ'NLP/NVP'ꢀproductꢀfamilyꢀfeatureꢀhigh-speed,ꢀ

low-powerꢀsynchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀ

aꢀburstable,ꢀhigh-performance,ꢀ'noꢀwait'ꢀstate,ꢀdeviceꢀforꢀ

networkingꢀandꢀcommunicationsꢀapplications.ꢀTheyꢀareꢀ

organizedꢀasꢀ128Kꢀwordsꢀbyꢀ32ꢀbits,ꢀ128Kꢀwordsꢀbyꢀ36ꢀ

bits,ꢀandꢀ256Kꢀꢀwordsꢀbyꢀ18ꢀbits,ꢀfabricatedꢀwithꢀISSI'sꢀ

advanced CMOS technology.

•ꢀ 100ꢀpercentꢀbusꢀutilization

•ꢀ NoꢀwaitꢀcyclesꢀbetweenꢀReadꢀandꢀWrite

•ꢀ Internalꢀself-timedꢀwriteꢀcycle

•ꢀ IndividualꢀByteꢀWriteꢀControl

•ꢀ SingleꢀR/Wꢀ(Read/Write)ꢀcontrolꢀpin

•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀꢀ

ꢀ

Incorporatingꢀ aꢀ 'noꢀ wait'ꢀ stateꢀ feature,ꢀ waitꢀ cyclesꢀ areꢀ

eliminated when the bus switches from read to write, or

writeꢀtoꢀread.ꢀThisꢀdeviceꢀintegratesꢀaꢀ2-bitꢀburstꢀcounter,ꢀ

high-speedꢀSRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀ

into a single monolithic circuit.

data and control

•ꢀ Interleavedꢀorꢀlinearꢀburstꢀsequenceꢀcontrolꢀus-

ing MODE input

•ꢀ Threeꢀchipꢀenablesꢀforꢀsimpleꢀdepthꢀexpansionꢀ

Allsynchronousinputspassthroughregistersarecontrolled

byꢀaꢀpositive-edge-triggeredꢀsingleꢀclockꢀinput.ꢀOperationsꢀ

may be suspended and all synchronous inputs ignored

when Clock Enable, CKEꢀisꢀHIGH.ꢀInꢀthisꢀstateꢀtheꢀinternalꢀ

device will hold their previous values.

and address pipelining

•ꢀ PowerꢀDownꢀmode

•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs

•ꢀ CKE pin to enable clock and suspend operation

AllꢀRead,ꢀWriteꢀandꢀDeselectꢀcyclesꢀareꢀinitiatedꢀbyꢀtheꢀADVꢀ

input.ꢀWhenꢀtheꢀADVꢀisꢀHIGHꢀtheꢀinternalꢀburstꢀcounterꢀ

isꢀincremented.ꢀNewꢀexternalꢀaddressesꢀcanꢀbeꢀloadedꢀ

whenꢀADVꢀisꢀLOW.

•ꢀ JEDECꢀ100-pinꢀTQFP,ꢀ165-ballꢀPBGAꢀandꢀ119-

ballꢀPBGAꢀpackages

•ꢀ Powerꢀsupply:

Writeꢀ cyclesꢀ areꢀ internallyꢀ self-timedꢀ andꢀ areꢀ initiatedꢀ

by the rising edge of the clock inputs and when WE is

LOW.ꢀSeparateꢀbyteꢀenablesꢀallowꢀindividualꢀbytesꢀtoꢀbeꢀ

written.

NVP:ꢀV^{d d}2.5Vꢀ(±ꢀ5%),ꢀVd d q ꢀ2.5Vꢀ(±ꢀ5%)

NLP:ꢀV^{d d}ꢀ3.3Vꢀ(±ꢀ5%),ꢀVd d q ꢀ3.3V/2.5Vꢀ(±ꢀ5%)

•ꢀ Industrialꢀtemperatureꢀavailable

•ꢀ Lead-freeꢀavailable

ꢀAꢀburstꢀmodeꢀpinꢀ(MODE)ꢀdeﬁnesꢀtheꢀorderꢀofꢀtheꢀburstꢀ

sequence.ꢀWhenꢀtiedꢀHIGH,ꢀtheꢀinterleavedꢀburstꢀsequenceꢀ

isꢀselected.ꢀWhenꢀtiedꢀLOW,ꢀtheꢀlinearꢀburstꢀsequenceꢀisꢀ

selected.

FAST ACCESS TIME

Symbol

Parameter

-250

2.6ꢀ

4ꢀ

-200

3.1ꢀ

5ꢀ

Units

tk q ꢀ

tk c ꢀ

ꢀ

ClockꢀAccessꢀTimeꢀ

CycleꢀTimeꢀ

ꢀ

Frequencyꢀ

250ꢀ

200ꢀ

MHz

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device speciﬁcation before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com

Rev. D

09/10/07

12 3 4 5 6 7...29

中文翻译

下载PDF

与IS61NLP12832B-200B2相关器件

型号	品牌	获取价格	描述	数据表
IS61NLP12832B-200B2I	ISSI	获取价格	128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM
IS61NLP12832B-200B3	ISSI	获取价格	128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM
IS61NLP12832B-200B3I	ISSI	获取价格	128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM
IS61NLP12832B-200TQ	ISSI	获取价格	128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM
IS61NLP12832B-200TQI	ISSI	获取价格	128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM
IS61NLP12832B-200TQLI	ISSI	获取价格	128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM
IS61NLP12832B-250B2	ISSI	获取价格	128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM
IS61NLP12832B-250B2I	ISSI	获取价格	128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM
IS61NLP12832B-250B3	ISSI	获取价格	128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM
IS61NLP12832B-250B3I	ISSI	获取价格	128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM

与IS61NLP12832B-200B2相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

17
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

12
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

42
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

36

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61NLP12832B-200B2

IS61NLP12832B-200B2 数据手册

与IS61NLP12832B-200B2相关器件

与IS61NLP12832B-200B2相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IS61NLP12832B-200B2

IS61NLP12832B-200B2 数据手册

与IS61NLP12832B-200B2相关器件

与IS61NLP12832B-200B2相关文章

您还可以找

您在本页遇到什么问题？