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IS61NLP12832B-250TQ PDF预览

IS61NLP12832B-250TQ

更新时间： 2024-11-18 05:39:35
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
29页 445K
描述
128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM

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IS61NLP12832B-250TQ 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TQFP-100针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.8
Is Samacsys：N最长访问时间：2.6 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：250 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：4194304 bit内存集成电路类型：ZBT SRAM
内存宽度：32湿度敏感等级：3
功能数量：1端子数量：100
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：128KX32
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.03 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.225 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

IS61NLP12832B-250TQ 数据手册

 浏览型号IS61NLP12832B-250TQ的Datasheet PDF文件第2页浏览型号IS61NLP12832B-250TQ的Datasheet PDF文件第3页浏览型号IS61NLP12832B-250TQ的Datasheet PDF文件第4页浏览型号IS61NLP12832B-250TQ的Datasheet PDF文件第5页浏览型号IS61NLP12832B-250TQ的Datasheet PDF文件第6页浏览型号IS61NLP12832B-250TQ的Datasheet PDF文件第7页 
IS61NLP12832B  
IS61NLP12836B/IS61NVP12836B  
IS61NLP25618A/IS61NVP25618A  
128K x 32, 128K x 36, and 256K x 18  
4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM  
SEPTEMBER 2007  
FEATURES  
DESCRIPTION  
Theꢀ4ꢀMegꢀ'NLP/NVP'ꢀproductꢀfamilyꢀfeatureꢀhigh-speed,ꢀ  
low-powerꢀsynchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀ  
aꢀburstable,ꢀhigh-performance,ꢀ'noꢀwait'ꢀstate,ꢀdeviceꢀforꢀ  
networkingꢀandꢀcommunicationsꢀapplications.ꢀTheyꢀareꢀ  
organizedꢀasꢀ128Kꢀwordsꢀbyꢀ32ꢀbits,ꢀ128Kꢀwordsꢀbyꢀ36ꢀ  
bits,ꢀandꢀ256Kꢀꢀwordsꢀbyꢀ18ꢀbits,ꢀfabricatedꢀwithꢀISSI'sꢀ  
advanced CMOS technology.  
•ꢀ 100ꢀpercentꢀbusꢀutilization  
•ꢀ NoꢀwaitꢀcyclesꢀbetweenꢀReadꢀandꢀWrite  
•ꢀ Internalꢀself-timedꢀwriteꢀcycle  
•ꢀ IndividualꢀByteꢀWriteꢀControl  
•ꢀ SingleꢀR/Wꢀ(Read/Write)ꢀcontrolꢀpin  
•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀꢀ  
ꢀ
Incorporatingꢀ aꢀ 'noꢀ wait'ꢀ stateꢀ feature,ꢀ waitꢀ cyclesꢀ areꢀ  
eliminated when the bus switches from read to write, or  
writeꢀtoꢀread.ꢀThisꢀdeviceꢀintegratesꢀaꢀ2-bitꢀburstꢀcounter,ꢀ  
high-speedꢀSRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀ  
into a single monolithic circuit.  
data and control  
•ꢀ Interleavedꢀorꢀlinearꢀburstꢀsequenceꢀcontrolꢀus-  
ing MODE input  
•ꢀ Threeꢀchipꢀenablesꢀforꢀsimpleꢀdepthꢀexpansionꢀ  
Allsynchronousinputspassthroughregistersarecontrolled  
byꢀaꢀpositive-edge-triggeredꢀsingleꢀclockꢀinput.ꢀOperationsꢀ  
may be suspended and all synchronous inputs ignored  
when Clock Enable, CKEꢀisꢀHIGH.ꢀInꢀthisꢀstateꢀtheꢀinternalꢀ  
device will hold their previous values.  
and address pipelining  
•ꢀ PowerꢀDownꢀmode  
•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs  
•ꢀ CKE pin to enable clock and suspend operation  
AllꢀRead,ꢀWriteꢀandꢀDeselectꢀcyclesꢀareꢀinitiatedꢀbyꢀtheꢀADVꢀ  
input.ꢀWhenꢀtheꢀADVꢀisꢀHIGHꢀtheꢀinternalꢀburstꢀcounterꢀ  
isꢀincremented.ꢀNewꢀexternalꢀaddressesꢀcanꢀbeꢀloadedꢀ  
whenꢀADVꢀisꢀLOW.  
•ꢀ JEDECꢀ100-pinꢀTQFP,ꢀ165-ballꢀPBGAꢀandꢀ119-  
ballꢀPBGAꢀpackages  
•ꢀ Powerꢀsupply:  
Writeꢀ cyclesꢀ areꢀ internallyꢀ self-timedꢀ andꢀ areꢀ initiatedꢀ  
by the rising edge of the clock inputs and when WE is  
LOW.ꢀSeparateꢀbyteꢀenablesꢀallowꢀindividualꢀbytesꢀtoꢀbeꢀ  
written.  
NVP:ꢀVd d 2.5Vꢀ(±ꢀ5%),ꢀVd d q ꢀ2.5Vꢀ(±ꢀ5%)  
NLP:ꢀVd d ꢀ3.3Vꢀ(±ꢀ5%),ꢀVd d q ꢀ3.3V/2.5Vꢀ(±ꢀ5%)  
•ꢀ Industrialꢀtemperatureꢀavailable  
•ꢀ Lead-freeꢀavailable  
ꢀAꢀburstꢀmodeꢀpinꢀ(MODE)ꢀdefinesꢀtheꢀorderꢀofꢀtheꢀburstꢀ  
sequence.ꢀWhenꢀtiedꢀHIGH,ꢀtheꢀinterleavedꢀburstꢀsequenceꢀ  
isꢀselected.ꢀWhenꢀtiedꢀLOW,ꢀtheꢀlinearꢀburstꢀsequenceꢀisꢀ  
selected.  
FAST ACCESS TIME  
Symbol  
Parameter  
-250  
2.6ꢀ  
4ꢀ  
-200  
3.1ꢀ  
5ꢀ  
Units  
ns  
tk q ꢀ  
tk c ꢀ  
ꢀ
ClockꢀAccessꢀTimeꢀ  
CycleꢀTimeꢀ  
ns  
ꢀ
Frequencyꢀ  
250ꢀ  
200ꢀ  
MHz  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no  
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on  
any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com  
1
Rev. D  
09/10/07  
1234567...29

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与IS61NLP12832B-250TQ相关器件

型号 品牌 获取价格 描述 数据表
IS61NLP12832B-250TQI ISSI

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 		128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM
IS61NLP12836 ISSI

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 		PIPELINE NO WAIT STATE BUS SRAM
IS61NLP12836-100TQ ISSI

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 		ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, TQFP-100
IS61NLP12836-133B ISSI

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 		PIPELINE NO WAIT STATE BUS SRAM
IS61NLP12836-133TQ ISSI

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 		PIPELINE NO WAIT STATE BUS SRAM
IS61NLP12836-5B ISSI

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 		PIPELINE NO WAIT STATE BUS SRAM
IS61NLP12836-5TQ ISSI

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 		PIPELINE NO WAIT STATE BUS SRAM
IS61NLP12836-5TQI ISSI

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 		PIPELINE NO WAIT STATE BUS SRAM
IS61NLP12836A ISSI

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 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP12836A-200B2 ISSI

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 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM

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