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IS61NLP12832-5B PDF预览

IS61NLP12832-5B

更新时间： 2024-11-19 22:10:11
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器
页数 文件大小 规格书
20页 156K
描述
PIPELINE NO WAIT STATE BUS SRAM

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IS61NLP12832-5B 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：PLASTIC, BGA-119针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.8
最长访问时间：5 ns最大时钟频率 (fCLK)：100 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：4194304 bit内存集成电路类型：ZBT SRAM
内存宽度：32功能数量：1
端子数量：119字数：131072 words
字数代码：128000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：128KX32输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119,7X17,50封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：240电源：2.5,3.3 V
认证状态：Not Qualified座面最大高度：2.41 mm
最大待机电流：0.02 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.3 mA
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：14 mm
Base Number Matches：1

IS61NLP12832-5B 数据手册

 浏览型号IS61NLP12832-5B的Datasheet PDF文件第2页浏览型号IS61NLP12832-5B的Datasheet PDF文件第3页浏览型号IS61NLP12832-5B的Datasheet PDF文件第4页浏览型号IS61NLP12832-5B的Datasheet PDF文件第5页浏览型号IS61NLP12832-5B的Datasheet PDF文件第6页浏览型号IS61NLP12832-5B的Datasheet PDF文件第7页 
®
IS61NP12832 IS61NP12836 IS61NP25618  
IS61NLP12832 IS61NLP12836 IS61NLP25618 ISSI  
128K x 32, 128K x 36 and 256K x 18  
PIPELINE 'NO WAIT' STATE BUS SRAM  
PRELIMINARY INFORMATION  
OCTOBER 2000  
FEATURES  
DESCRIPTION  
The 4 Meg 'NP' product family feature high-speed,  
low-power synchronous static RAMs designed to provide  
a burstable, high-performance, 'no wait' state, device for  
network and communications customers. They are  
organized as 131,072 words by 32 bits, 131,072 words  
by 36 bits and 262,144 words by 18 bits, fabricated with  
ISSI's advanced CMOS technology.  
• 100 percent bus utilization  
• No wait cycles between Read and Write  
• Internal self-timed write cycle  
• Individual Byte Write Control  
• Single R/W (Read/Write) control pin  
• Clock controlled, registered address,  
data and control  
Incorporating a 'no wait' state feature, wait cycles are  
eliminated when the bus switches from read to write, or  
write to read. This device integrates a 2-bit burst counter,  
high-speed SRAM core, and high-drive capability outputs  
into a single monolithic circuit.  
• Interleaved or linear burst sequence control  
using MODE input  
• Three chip enables for simple depth expansion  
and address pipelining for TQFP  
Allsynchronousinputspassthroughregistersarecontrolled  
byapositive-edge-triggeredsingleclockinput.Operations  
may be suspended and all synchronous inputs ignored  
when Clock Enable, CKE is HIGH. In this state the internal  
device will hold their previous values.  
• Power Down mode  
• Common data inputs and data outputs  
• CKE pin to enable clock and suspend operation  
• JEDEC 100-pin TQFP, 119 PBGA package  
• Single +3.3V power supply (± 5%)  
• NP Version: 3.3V I/O Supply Voltage  
• NLP Version: 2.5V I/O Supply Voltage  
• Industrialtemperatureavailable  
All Read, Write and Deselect cycles are initiated by the  
ADV input. When the ADV is HIGH the internal burst  
counter is incremented. New external addresses can be  
loaded when ADV is LOW.  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock inputs and when WE is LOW.  
Separate byte enables allow individual bytes to be written.  
A burst mode pin (MODE) defines the order of the burst  
sequence.WhentiedHIGH,theinterleavedburstsequence  
is selected. When tied LOW, the linear burst sequence is  
selected.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-150*  
3.8  
-133  
4.2  
-100  
5
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
6.7  
7.5  
10  
ns  
Frequency  
150  
133  
100  
MHz  
*This speed available only in NP version  
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the  
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
PRELIMINARY INFORMATION Rev. 00C  
1
11/30/00  
1234567...20

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与IS61NLP12832-5B相关器件

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IS61NLP12832-5TQ ISSI

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IS61NLP12832-5TQI ISSI

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 		PIPELINE NO WAIT STATE BUS SRAM
IS61NLP12832A ISSI

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 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP12832A-200B2 ISSI

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 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP12832A-200B2I ISSI

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 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP12832A-200B3 ISSI

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 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP12832A-200B3I ISSI

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 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP12832A-200TQ ISSI

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 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP12832A-200TQI ISSI

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 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NLP12832A-200TQLI ISSI

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 		128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM

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