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IS61LV256-20N PDF预览

IS61LV256-20N

更新时间: 2024-01-11 09:31:32
品牌 Logo 应用领域
美国芯成 - ISSI /
页数 文件大小 规格书
8页 103K
描述
32K x 8 LOW VOLTAGE CMOS STATIC RAM

IS61LV256-20N 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSOP
包装说明:TSOP1-28针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.25
最长访问时间:20 ns其他特性:AUTOMATIC POWER DOWN
I/O 类型:COMMONJESD-30 代码:R-PDSO-G28
JESD-609代码:e0内存密度:262144 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:28字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:32KX8输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:TSOP1封装等效代码:TSSOP28,.53,22
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL认证状态:Not Qualified
反向引出线:NO最大待机电流:0.005 A
最大压摆率:0.09 mA最大供电电压 (Vsup):3.33 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子位置:DUAL
Base Number Matches:1

IS61LV256-20N 数据手册

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®
IS61LV256  
32K x 8 LOW VOLTAGE CMOS STATIC RAM  
ISSI  
FEBRUARY 1996  
FEATURES  
DESCRIPTION  
The ISSI IS61LV256 is a very high-speed, low power,  
32,768-word by 8-bit static RAM. It is fabricated using ISSI's  
high-performance CMOS technology. This highly reliable pro-  
cess coupled with innovative circuit design techniques, yields  
access times as fast as 12 ns maximum.  
• High-speed access time: 12, 15, 20, 25 ns  
• Automatic power-down when chip is deselected  
• CMOS low power operation  
— 345 mW (max.) operating  
— 7 mW (max.) CMOS standby  
• TTL compatible interface levels  
• Single 3.3V power supply  
WhenCEisHIGH(deselected),thedeviceassumesastandby  
mode at which the power dissipation is reduced to  
50 µW (typical) with CMOS input levels.  
• Fully static operation: no clock or refresh  
required  
Easy memory expansion is provided by using an active LOW  
ChipEnable(CE).TheactiveLOWWriteEnable(WE)controls  
both writing and reading of the memory.  
• Three-state outputs  
The IS61LV256 is available in the JEDEC standard 28-pin,  
300-mil DIP and SOJ, plus the 450-mil TSOP package.  
FUNCTIONAL BLOCK DIAGRAM  
256 X 1024  
MEMORY ARRAY  
A0-A14  
DECODER  
VCC  
GND  
I/O  
DATA  
COLUMN I/O  
I/O0-I/O7  
CIRCUIT  
CE  
CONTROL  
CIRCUIT  
OE  
WE  
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which  
may appear in this publication. © Copyright 1996, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc.  
2-1  
Rev. F 0296  
SR81995LV61  

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