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IS61LPS25618A-250B3 PDF预览

IS61LPS25618A-250B3

更新时间： 2024-09-25 04:58:35
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
26页 167K
描述
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

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IS61LPS25618A-250B3 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：BGA
包装说明：TBGA, BGA165,11X15,40针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.49
Is Samacsys：N最长访问时间：2.6 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：250 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B165
JESD-609代码：e0长度：15 mm
内存密度：4718592 bit内存集成电路类型：CACHE SRAM
内存宽度：18功能数量：1
端子数量：165字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256KX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大待机电流：0.00007 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.225 mA
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：13 mm
Base Number Matches：1

IS61LPS25618A-250B3 数据手册

 浏览型号IS61LPS25618A-250B3的Datasheet PDF文件第2页浏览型号IS61LPS25618A-250B3的Datasheet PDF文件第3页浏览型号IS61LPS25618A-250B3的Datasheet PDF文件第4页浏览型号IS61LPS25618A-250B3的Datasheet PDF文件第5页浏览型号IS61LPS25618A-250B3的Datasheet PDF文件第6页浏览型号IS61LPS25618A-250B3的Datasheet PDF文件第7页 
IS61(64)LPS12832A  
IS61(64)LPS12836A IS61(64)VPS12836A  
IS61(64)LPS25618A IS61(64)VPS25618A  
®
ISSI  
128K x 32, 128K x 36, 256K x 18  
4 Mb SYNCHRONOUS PIPELINED,  
SINGLE CYCLE DESELECT STATIC RAM  
PRELIMINARY INFORMATION  
FEBRUARY 2005  
DESCRIPTION  
FEATURES  
The ISSIIS61(64)LPS12832A,IS61(64)LPS/VPS12836A  
andIS61(64)LPS/VPS25618Aarehigh-speed,low-power  
synchronous static RAMs designed to provide burstable,  
high-performancememoryforcommunicationandnetwork-  
ingapplications.TheIS61(64)LPS12832Aisorganizedas  
131,072wordsby32bits.TheIS61(64)LPS/VPS12836A  
isorganizedas131,072wordsby36bits.TheIS61(64)LPS/  
VPS25618A is organized as 262,144 words by 18 bits.  
Fabricated with ISSI's advanced CMOS technology, the  
deviceintegratesa2-bitburstcounter,high-speedSRAM  
core,andhigh-drivecapabilityoutputsintoasinglemono-  
lithic circuit. All synchronous inputs pass through regis-  
ters controlled by a positive-edge-triggered single clock  
input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Burst sequence control using MODE input  
• Three chip enable option for simple depth  
expansion and address pipelining  
• Common data inputs and data outputs  
• Auto Power-down during deselect  
• Single cycle deselect  
Write cycles are internally self-timed and are initiated by  
therisingedgeoftheclockinput. Writecyclescanbeone  
tofourbyteswideascontrolledbythewritecontrolinputs.  
• Snooze MODE for reduced-power standby  
• Power Supply  
Separatebyteenablesallowindividualbytestobewritten.  
The byte write operation is performed by using the byte  
write enable (BWE) input combined with one or more  
individual byte write signals (BWx). In addition, Global  
Write (GW) is available for writing all bytes at one time,  
regardless of the byte write controls.  
LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%  
VPS: VDD 2.5V + 5%, VDDQ 2.5V + 5%  
• JEDEC 100-Pin TQFP, 119-ball PBGA, and  
165-ball PBGA packages  
• Automotive temperature available  
• Lead Free available  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
inputpins.Subsequentburstaddressescanbegenerated  
internally and controlled by the ADV (burst address  
advance) input pin.  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW.  
Interleave burst is achieved when this pin is tied HIGH or  
left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
250  
2.6  
4
200  
3.1  
5
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
ns  
Frequency  
250  
200  
MHz  
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability  
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany  
publishedinformationandbeforeplacingordersforproducts.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. 00A  
1
10/07/04  
1234567...26

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与IS61LPS25618A-250B3相关器件

型号 品牌 获取价格 描述 数据表
IS61LPS25618A-250B3I ISSI

获取价格

 		128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC R
IS61LPS25618A-250TQ ISSI

获取价格

 		128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC R
IS61LPS25618A-250TQI ISSI

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 		128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC R
IS61LPS25618EC-200B2 ISSI

获取价格

 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS61LPS25618EC-200B2I ISSI

获取价格

 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS61LPS25618EC-200B2L ISSI

获取价格

 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS61LPS25618EC-200B2LI ISSI

获取价格

 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS61LPS25618EC-200B3 ISSI

获取价格

 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS61LPS25618EC-200B3I ISSI

获取价格

 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM
IS61LPS25618EC-200B3L ISSI

获取价格

 		128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM

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