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IS61LPD51218A-200B2I PDF预览

IS61LPD51218A-200B2I

更新时间： 2024-11-11 04:58:35
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
32页 208K
描述
256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

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中文翻译

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IS61LPD51218A-200B2I 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：BGA
包装说明：BGA, BGA119,7X17,50针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.53
Is Samacsys：N最长访问时间：3.1 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：200 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：9437184 bit内存集成电路类型：CACHE SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：119
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA119,7X17,50
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：2.41 mm最大待机电流：0.06 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.275 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

IS61LPD51218A-200B2I 数据手册

 浏览型号IS61LPD51218A-200B2I的Datasheet PDF文件第2页浏览型号IS61LPD51218A-200B2I的Datasheet PDF文件第3页浏览型号IS61LPD51218A-200B2I的Datasheet PDF文件第4页浏览型号IS61LPD51218A-200B2I的Datasheet PDF文件第5页浏览型号IS61LPD51218A-200B2I的Datasheet PDF文件第6页浏览型号IS61LPD51218A-200B2I的Datasheet PDF文件第7页 
®
IS61VPD25636A IS61LPD25636A  
IS61VPD51218A IS61LPD51218A  
ISSI  
256K x 36, 512K x 18  
9 Mb SYNCHRONOUS PIPELINED,  
DOUBLE CYCLE DESELECT STATIC RAM  
MAY 2005  
DESCRIPTION  
FEATURES  
The ISSIIS61LPD/VPD25636AandIS61LPD/VPD51218A  
are high-speed, low-power synchronous static RAMs de-  
signed to provide burstable, high-performance memory for  
communicationandnetworkingapplications.TheIS61LPD/  
VPD25636Aisorganizedas262,144wordsby36bits,and  
the IS61LPD/VPD51218A is organized as 524,288 words  
by18bits.FabricatedwithISSI'sadvancedCMOStechnol-  
ogy,thedeviceintegratesa2-bitburstcounter,high-speed  
SRAM core, and high-drive capability outputs into a single  
monolithic circuit. All synchronous inputs pass through  
registers controlled by a positive-edge-triggered single  
clock input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Burst sequence control using MODE input  
• Three chip enable option for simple depth  
expansion and address pipelining  
• Common data inputs and data outputs  
• Auto Power-down during deselect  
• Double cycle deselect  
Writecyclesareinternallyself-timedandareinitiatedbythe  
risingedgeoftheclockinput.Writecyclescanbeonetofour  
bytes wide as controlled by the write control inputs.  
• Snooze MODE for reduced-power standby  
• JTAG Boundary Scan for PBGA package  
• Power Supply  
Separate byte enables allow individual bytes to be written.  
The byte write operation is performed by using the byte  
write enable (BWE) input combined with one or more  
individual byte write signals (BWx). In addition, Global  
Write (GW) is available for writing all bytes at one time,  
regardless of the byte write controls.  
LPD: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%  
VPD: VDD 2.5V + 5%, VDDQ 2.5V + 5%  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally and controlled by the ADV (burst address  
advance) input pin.  
• JEDEC 100-Pin TQFP,  
119-pin PBGA and 165-pin PBGA package  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW.  
Interleave burst is achieved when this pin is tied HIGH or  
left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
250  
2.6  
4
200  
3.1  
5
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
ns  
Frequency  
250  
200  
MHz  
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability  
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany  
publishedinformationandbeforeplacingordersforproducts.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
1
05/09/05  
1234567...32

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与IS61LPD51218A-200B2I相关器件

型号 品牌 获取价格 描述 数据表
IS61LPD51218A-200B3 ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61LPD51218A-200B3I ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61LPD51218A-200TQ ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61LPD51218A-200TQI ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61LPD51218A-250B2 ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61LPD51218A-250B2I ISSI

获取价格

 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61LPD51218A-250B3 ISSI

获取价格

 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61LPD51218A-250B3I ISSI

获取价格

 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61LPD51218A-250TQ ISSI

获取价格

 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM
IS61LPD51218A-250TQI ISSI

获取价格

 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

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