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IS61LPD25632D-250TQ PDF预览

IS61LPD25632D-250TQ

更新时间： 2024-11-11 15:35:31
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
29页 172K
描述
Cache SRAM, 256KX32, 2.6ns, CMOS, PQFP100, TQFP-100

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IS61LPD25632D-250TQ 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TQFP-100针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.92
最长访问时间：2.6 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：250 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
长度：20 mm内存密度：8388608 bit
内存集成电路类型：CACHE SRAM内存宽度：32
功能数量：1端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256KX32
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：240
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.03 A
最小待机电流：3.14 V子类别：SRAMs
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：14 mm
Base Number Matches：1

IS61LPD25632D-250TQ 数据手册

 浏览型号IS61LPD25632D-250TQ的Datasheet PDF文件第2页浏览型号IS61LPD25632D-250TQ的Datasheet PDF文件第3页浏览型号IS61LPD25632D-250TQ的Datasheet PDF文件第4页浏览型号IS61LPD25632D-250TQ的Datasheet PDF文件第5页浏览型号IS61LPD25632D-250TQ的Datasheet PDF文件第6页浏览型号IS61LPD25632D-250TQ的Datasheet PDF文件第7页 
IS61LPD25632T/D/J  
IS61LPD25636T/D/J  
IS61LPD51218T/D/J  
®
ISSI  
256K x 32, 256K x 36, 512K x 18  
SYNCHRONOUS PIPELINED,  
APRIL 2003  
DOUBLE-CYCLE DESELECT STATIC RAM  
DESCRIPTION  
FEATURES  
The ISSI IS61LPD25632T/D/J,IS61LPD25636T/D/J,and  
IS61LPD51218T/D/Jare high-speed, low-power synchro-  
nous static RAMs designed to provide burstable, high-  
performance memory for communication and networking  
applications. The IS61LPD25632T/D/J is organized as  
262,144 words by 32 bits and the IS61LPD25636T/D/J is  
organizedas262,144wordsby36bits.TheIS61LPD51218T/  
D/J is organized as 524,288 words by 18 bits. Fabricated  
with ISSI's advanced CMOS technology, the device inte-  
grates a 2-bit burst counter, high-speed SRAM core, and  
high-drivecapabilityoutputsintoasinglemonolithiccircuit.  
Allsynchronousinputspassthroughregisterscontrolledby  
a positive-edge-triggered single clock input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Linear burst sequence control using MODE  
input  
•
Three chip enable option for simple depth  
expansion and address pipelining  
• Common data inputs and data outputs  
• JEDEC 100-Pin TQFP and  
119-pin PBGA package  
Writecyclesareinternallyself-timedandareinitiatedbythe  
risingedgeoftheclockinput.Writecyclescanbeonetofour  
bytes wide as controlled by the write control inputs.  
• Power Supply  
+3.3V VDD  
Separate byte enables allow individual bytes to be written.  
Bytewriteoperationisperformedbyusingbytewriteenable  
(BWE). Input combined with one or more individual byte  
write signals (BWx). In addition, Global Write (GW) is  
available for writing all bytes at one time, regardless of the  
byte write controls.  
+3.3V or 2.5 VDDQ (I/O)  
• Auto Power-down during deselect  
• Double cycle deselect  
• Snooze MODE for reduced-power standby  
• JTAG Boundary Scan for PBGA package  
• T Version (three chips selects)  
• D Version (two chips selects)  
• J Version (PBGA Package with JTAG)  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally and controlled by the ADV (burst address ad-  
vance) input pin.  
The mode pin is used to select the burst sequence order.  
Linear burst is achieved when this pin is tied LOW. Inter-  
leave burst is achieved when this pin is tied HIGH or left  
floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-250  
2.6  
4
-225  
2.8  
-200  
3.1  
5
-166  
3.5  
6
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
4.4  
ns  
Frequency  
250  
225  
200  
166  
MHz  
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
1
04/01/03  
1234567...29

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与IS61LPD25632D-250TQ相关器件

型号 品牌 获取价格 描述 数据表
IS61LPD25632D-5B ISSI

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 		Cache SRAM, 256KX32, 5ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61LPD25632D-5TQ ISSI

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 		Cache SRAM, 256KX32, 5ns, CMOS, PQFP100, TQFP-100
IS61LPD25632D-5TQI ISSI

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 		Cache SRAM, 256KX32, 5ns, CMOS, PQFP100, TQFP-100
IS61LPD25632T/D ISSI

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 		256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE, DOUBLE-CYCLE DESELECT STATIC RAM
IS61LPD25632T-150TQ ISSI

获取价格

 		Cache SRAM, 256KX32, 3.8ns, CMOS, PQFP100, TQFP-100
IS61LPD25632T-200TQ ISSI

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 		Cache SRAM, 256KX32, 3.1ns, CMOS, PQFP100, TQFP-100
IS61LPD25632T-200TQI ISSI

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 		Cache SRAM, 256KX32, 3.1ns, CMOS, PQFP100, TQFP-100
IS61LPD25632T-225TQI ISSI

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 		Cache SRAM, 256KX32, 2.8ns, CMOS, PQFP100, TQFP-100
IS61LPD25632T-5TQI ISSI

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 		Cache SRAM, 256KX32, 5ns, CMOS, PQFP100, TQFP-100
IS61LPD25636A ISSI

获取价格

 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM

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