Datasheet > IS43LR16200C-6BL

IS43LR16200C-6BL

更新时间： 2024-11-28 01:11:51

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
42页	1814K
描述
JEDEC standard 1.8V power supply

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IS43LR16200C-6BL 数据手册

IS43LR16200C

1M x 16Bits x 2Banks Mobile DDR SDRAM

Description

The IS43LR16200C is 33,554,432 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 2 banks of 1,048,576 words x 16 bits.

This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2N

prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully

synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched

to achieve high bandwidth. All input and output voltage levels are compatible with LVCMOS.

Features

• JEDEC standard 1.8V power supply

• Two internal banks for concurrent operation

• MRS cycle with address key programs

- CAS latency 2, 3 (clock)

• 64ms refresh period (4K cycle)

• Auto & self refresh

• Concurrent Auto Precharge

• Maximum clock frequency up to 166MHz

• Maximum data rate up to 333Mbps/pin

• Power Saving support

- Burst length (2, 4, 8, 16)

- Burst type (sequential & interleave)

• Fully differential clock inputs (CK, /CK)

• All inputs except data & DM are sampled at the rising

edge of the system clock

- PASR (Partial Array Self Refresh)

- Auto TCSR (Temperature Compensated Self Refresh)

- Deep Power Down Mode

• Data I/O transaction on both edges of data strobe

• Bidirectional data strobe per byte of data (DQS)

• DM for write masking only

- Programmable Driver Strength Control by Full Strength

or 1/2, 1/4, 1/8 of Full Strength

• LVCMOS compatible inputs/outputs

• Edge aligned data & data strobe output

• Center aligned data & data strobe input

roducts at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services de

scribed herein. Customers are advised to obtain the latest version of this device specification before relying on any published information a

nd before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or

malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or

effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to

its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

www.issi.com - dram@issi.com

Rev. A | March 2013

12 3 4 5 6 7...42

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与IS43LR16200C-6BL相关器件

型号	品牌	获取价格	描述	数据表
IS43LR16200C-6BLI	ISSI	获取价格	JEDEC standard 1.8V power supply
IS43LR16320B	ISSI	获取价格	8M x 16Bits x 4Banks Mobile DDR SDRAM
IS43LR16320B-6BL	ISSI	获取价格	DDR DRAM, 32MX16, 5.5ns, CMOS, PBGA60, 8 X 10 MM, LEAD FREE, MO-207, TFBGA-60
IS43LR16320B-6BLI	ISSI	获取价格	8M x 16Bits x 4Banks Mobile DDR SDRAM
IS43LR16320C-5BLI	ISSI	获取价格	DDR DRAM, 32MX16, 5ns, CMOS, PBGA60, 8 X 10 MM, LEAD FREE, MO-207, TFBGA-60
IS43LR16320C-5BLI-TR	ISSI	获取价格	DDR DRAM,
IS43LR16320C-6BLI	ISSI	获取价格	DDR DRAM, 32MX16, 5.5ns, CMOS, PBGA60, 8 X 10 MM, LEAD FREE, MO-207, TFBGA-60
IS43LR16400C-6BLI	ISSI	获取价格	DDR DRAM, 4MX16, 5.5ns, CMOS, PBGA60, 8 X 10 MM, LEAD FREE, MO-207, TFBGA-60
IS43LR16640A-5BL	ISSI	获取价格	DDR DRAM, 64MX16, 5ns, CMOS, PBGA60, 8 X 10 MM, LEAD FREE, MO-207, TFBGA-60
IS43LR16640A-5BLI	ISSI	获取价格	IC DRAM 1G PARALLEL 60TWBGA

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