Datasheet > IS43LR16640A-5BL

IS43LR16640A-5BL

更新时间： 2024-11-29 20:53:27

品牌	Logo	应用领域
美国芯成 - ISSI		时钟动态存储器双倍数据速率内存集成电路
页数	文件大小	规格书
43页	1169K
描述
DDR DRAM, 64MX16, 5ns, CMOS, PBGA60, 8 X 10 MM, LEAD FREE, MO-207, TFBGA-60

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

IS43LR16640A-5BL 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	DSBGA	包装说明：	TFBGA, BGA60,9X10,32
针数：	60	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.32
Factory Lead Time：	12 weeks	风险等级：	5.72
访问模式：	FOUR BANK PAGE BURST	最长访问时间：	5 ns
其他特性：	AUTO/SELF REFRESH	最大时钟频率 (fCLK)：	200 MHz
I/O 类型：	COMMON	交错的突发长度：	2,4,8
JESD-30 代码：	R-PBGA-B60	长度：	10 mm
内存密度：	1073741824 bit	内存集成电路类型：	DDR DRAM
内存宽度：	16	功能数量：	1
端口数量：	1	端子数量：	60
字数：	67108864 words	字数代码：	64000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	64MX16
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	TFBGA	封装等效代码：	BGA60,9X10,32
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, THIN PROFILE, FINE PITCH
电源：	1.8 V	认证状态：	Not Qualified
刷新周期：	8192	座面最大高度：	1.1 mm
自我刷新：	YES	连续突发长度：	2,4,8
最大待机电流：	0.005 A	子类别：	DRAMs
最大压摆率：	0.09 mA	最大供电电压 (Vsup)：	1.95 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	0.8 mm	端子位置：	BOTTOM
宽度：	8 mm	Base Number Matches：	1

IS43LR16640A-5BL 数据手册

IS43/46LR16640A

16M x 16Bits x 4Banks Mobile DDR SDRAM

Description

The IS43/46LR16640A is 1,073,741,824 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 16,777,216 words

x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted

on a 16-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data

words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock.

The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are

compatible with LVCMOS.

Features

• JEDEC standard 1.8V power supply.

• VDD = 1.8V, VDDQ = 1.8V

• 64ms refresh period (8K cycle)

• Auto & self refresh

• Four internal banks for concurrent operation

• MRS cycle with address key programs

- CAS latency 2, 3 (clock)

• Concurrent Auto Precharge

• Maximum clock frequency up to 200MHZ

• Maximum data rate up to 400Mbps/pin

• Power Saving support

- Burst length (2, 4, 8)

- Burst type (sequential & interleave)

• Fully differential clock inputs (CK, /CK)

• All inputs except data & DM are sampled at the rising

edge of the system clock

- PASR (Partial Array Self Refresh)

- Auto TCSR (Temperature Compensated Self Refresh)

- Deep Power Down Mode

- Programmable Driver Strength Control by Full Strength

or 1/2, 1/4, or 1/8 of Full Strength

• LVCMOS compatible inputs/outputs

• 60-Ball FBGA package

• Data I/O transaction on both edges of data strobe

• Bidirectional data strobe per byte of data (DQS)

• DM for write masking only

• Edge aligned data & data strobe output

• Center aligned data & data strobe input

products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services

described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information

and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or

malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or

effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to

its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

www.issi.com - dram@issi.com

Rev. B | March 2014

12 3 4 5 6 7...43

中文翻译

下载PDF

与IS43LR16640A-5BL相关器件

型号	品牌	获取价格	描述	数据表
IS43LR16640A-5BLI	ISSI	获取价格	IC DRAM 1G PARALLEL 60TWBGA
IS43LR16640A-5BLI-TR	ISSI	获取价格	IC DRAM 1G PARALLEL 60TWBGA
IS43LR16640A-5BL-TR	ISSI	获取价格	IC DRAM 1G PARALLEL 60TWBGA
IS43LR16640A-6BLI	ISSI	获取价格	IC DRAM 1G PARALLEL 60TWBGA
IS43LR16640A-6BLI-TR	ISSI	获取价格	IC DRAM 1G PARALLEL 60TWBGA
IS43LR16640A-6BL-TR	ISSI	获取价格	IC DRAM 1G PARALLEL 60TWBGA
IS43LR16800D-5BLI	ISSI	获取价格	DDR DRAM, 8MX16, 5ns, CMOS, PBGA60, 8 X 9 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-60
IS43LR16800D-6BL	ISSI	获取价格	DDR DRAM, 8MX16, 5.5ns, CMOS, PBGA60, 8 X 9 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-60
IS43LR16800D-6BLI	ISSI	获取价格	DDR DRAM, 8MX16, 5.5ns, CMOS, PBGA60, 8 X 9 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-60
IS43LR16800D-75BL	ISSI	获取价格	DDR DRAM, 8MX16, 6ns, CMOS, PBGA60, 8 X 9 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-60

与IS43LR16640A-5BL相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

49
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

39
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

67
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

63

产品中心

服务支持

精选活动

关于我们

帮助中心

IS43LR16640A-5BL

IS43LR16640A-5BL 技术参数

IS43LR16640A-5BL 数据手册

与IS43LR16640A-5BL相关器件

与IS43LR16640A-5BL相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IS43LR16640A-5BL

IS43LR16640A-5BL 技术参数

IS43LR16640A-5BL 数据手册

与IS43LR16640A-5BL相关器件

与IS43LR16640A-5BL相关文章

您还可以找

您在本页遇到什么问题？