Datasheet > IS43LR16320B

IS43LR16320B

更新时间： 2024-11-30 01:20:19

品牌	Logo	应用领域
美国芯成 - ISSI		动态存储器双倍数据速率
页数	文件大小	规格书
42页	2263K
描述
8M x 16Bits x 4Banks Mobile DDR SDRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IS43LR16320B 数据手册

IS43LR16320B, IS46LR16320B

8M x 16Bits x 4Banks Mobile DDR SDRAM

Description

The IS43/46LR16320B is a 536,870,912 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 8,388,608 words x

16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted

on a 16bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data

words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock.

The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are

compatible with LVCMOS.

Features

• JEDEC standard 1.8V power supply.

• VDD = 1.8V, VDDQ = 1.8V

• 64ms refresh period (8K cycle)

• Auto & self refresh

• Four internal banks for concurrent operation

• MRS cycle with address key programs

- CAS latency 2, 3 (clock)

• Concurrent Auto Precharge

• Maximum clock frequency up to 166MHZ

• Maximum data rate up to 333Mbps/pin

• Power Saving support

- Burst length (2, 4, 8, 16)

- Burst type (sequential & interleave)

• Fully differential clock inputs (CK, /CK)

• All inputs except data & DM are sampled at the rising

edge of the system clock

- PASR (Partial Array Self Refresh)

- Auto TCSR (Temperature Compensated Self Refresh)

- Deep Power Down Mode

- Programmable Driver Strength Control by Full Strength

or 1/2, 1/4, 1/8 of Full Strength

• Data I/O transaction on both edges of data strobe

• Bidirectional data strobe per byte of data (DQS)

• DM for write masking only

• LVCMOS compatible inputs/outputs

• 60-Ball FBGA package

• Edge aligned data & data strobe output

• Center aligned data & data strobe input

products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services

described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information

and before placing orders for products.

www.issi.com - dram@issi.com

Rev. A | Apr. 2012

12 3 4 5 6 7...42

中文翻译

下载PDF

与IS43LR16320B相关器件

型号	品牌	获取价格	描述	数据表
IS43LR16320B-6BL	ISSI	获取价格	DDR DRAM, 32MX16, 5.5ns, CMOS, PBGA60, 8 X 10 MM, LEAD FREE, MO-207, TFBGA-60
IS43LR16320B-6BLI	ISSI	获取价格	8M x 16Bits x 4Banks Mobile DDR SDRAM
IS43LR16320C-5BLI	ISSI	获取价格	DDR DRAM, 32MX16, 5ns, CMOS, PBGA60, 8 X 10 MM, LEAD FREE, MO-207, TFBGA-60
IS43LR16320C-5BLI-TR	ISSI	获取价格	DDR DRAM,
IS43LR16320C-6BLI	ISSI	获取价格	DDR DRAM, 32MX16, 5.5ns, CMOS, PBGA60, 8 X 10 MM, LEAD FREE, MO-207, TFBGA-60
IS43LR16400C-6BLI	ISSI	获取价格	DDR DRAM, 4MX16, 5.5ns, CMOS, PBGA60, 8 X 10 MM, LEAD FREE, MO-207, TFBGA-60
IS43LR16640A-5BL	ISSI	获取价格	DDR DRAM, 64MX16, 5ns, CMOS, PBGA60, 8 X 10 MM, LEAD FREE, MO-207, TFBGA-60
IS43LR16640A-5BLI	ISSI	获取价格	IC DRAM 1G PARALLEL 60TWBGA
IS43LR16640A-5BLI-TR	ISSI	获取价格	IC DRAM 1G PARALLEL 60TWBGA
IS43LR16640A-5BL-TR	ISSI	获取价格	IC DRAM 1G PARALLEL 60TWBGA

与IS43LR16320B相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

49
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

39
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

67
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

63

产品中心

服务支持

精选活动

关于我们

帮助中心

IS43LR16320B

IS43LR16320B 数据手册

与IS43LR16320B相关器件

与IS43LR16320B相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

IS43LR16320B

IS43LR16320B 数据手册

与IS43LR16320B相关器件

与IS43LR16320B相关文章

您还可以找

您在本页遇到什么问题？