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IS42VS16400C1-12T PDF预览

IS42VS16400C1-12T

更新时间: 2024-11-13 04:44:47
品牌 Logo 应用领域
美国芯成 - ISSI /
页数 文件大小 规格书
56页 491K
描述
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

IS42VS16400C1-12T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2, TSOP54,.46,32针数:54
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.02风险等级:5.81
访问模式:FOUR BANK PAGE BURST最长访问时间:9 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):83 MHz
I/O 类型:COMMON交错的突发长度:1,2,4,8
JESD-30 代码:R-PDSO-G54JESD-609代码:e0
长度:22.22 mm内存密度:67108864 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
湿度敏感等级:3功能数量:1
端口数量:1端子数量:54
字数:4194304 words字数代码:4000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP54,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED电源:1.8 V
认证状态:Not Qualified刷新周期:4096
座面最大高度:1.2 mm自我刷新:YES
连续突发长度:1,2,4,8,FP最大待机电流:0.0003 A
子类别:DRAMs最大压摆率:0.04 mA
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10.16 mm
Base Number Matches:1

IS42VS16400C1-12T 数据手册

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®
IS42VS16400C1  
ISSI  
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)  
SYNCHRONOUS DYNAMIC RAM  
OCTOBER 2005  
FEATURES  
OVERVIEW  
ISSI's 64Mb Synchronous DRAM IS42VS16400C1 is  
organized as 1,048,576 bits x 16-bit x 4-bank for improved  
performance.ThesynchronousDRAMsachievehigh-speed  
data transfer using pipeline architecture. All inputs and  
outputs signals refer to the rising edge of the clock input.  
• Clock frequency: 100, 83, 66 MHz  
• Fully synchronous; all signals referenced to a  
positive clock edge  
• Internal bank for hiding row access/precharge  
• Single 1.8V power supply  
• LVTTL interface  
PIN CONFIGURATIONS  
54-Pin TSOP (Type II)  
• Programmable burst length  
– (1, 2, 4, 8, full page)  
VDD  
DQ0  
VDDQ  
DQ1  
DQ2  
GNDQ  
DQ3  
DQ4  
VDDQ  
DQ5  
DQ6  
GNDQ  
DQ7  
VDD  
LDQM  
WE  
1
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
GND  
DQ15  
GNDQ  
DQ14  
DQ13  
VDDQ  
DQ12  
DQ11  
GNDQ  
DQ10  
DQ9  
VDDQ  
DQ8  
GND  
NC  
• Programmable burst sequence:  
Sequential/Interleave  
2
3
4
5
• Self refresh modes  
6
7
• 4096 refresh cycles every 64 ms  
• Random column address every clock cycle  
• Programmable CAS latency (2, 3 clocks)  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
• Burst read/write and burst read/single write  
operations capability  
UDQM  
CLK  
CKE  
NC  
CAS  
RAS  
CS  
• Burst termination by burst stop and precharge  
command  
BA0  
BA1  
A10  
A11  
A9  
A8  
• Byte controlled by LDQM and UDQM  
• Industrial temperature availability  
• Package: 400-mil 54-pin TSOP II  
• Lead-free package is available  
A0  
A7  
A1  
A6  
A2  
A5  
A3  
A4  
VDD  
GND  
PIN DESCRIPTIONS  
WE  
WriteEnable  
A0-A11  
BA0, BA1  
DQ0 to DQ15  
CLK  
Address Input  
LDQM  
UDQM  
VDD  
Lower Bye, Input/Output Mask  
Upper Bye, Input/Output Mask  
Power  
Bank Select Address  
Data I/O  
System Clock Input  
Clock Enable  
GND  
VDDQ  
GNDQ  
NC  
Ground  
CKE  
Power Supply for DQ Pin  
Ground for DQ Pin  
NoConnection  
CS  
Chip Select  
RAS  
RowAddressStrobeCommand  
ColumnAddressStrobeCommand  
CAS  
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no  
liabilityarisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingon  
anypublishedinformationandbeforeplacingordersforproducts.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
Rev. A  
1
10/06/05  

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