Datasheet > IS42VS16400E

IS42VS16400E

更新时间： 2024-11-14 01:03:51

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
58页	945K
描述
Random column address every clock cycle

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中文翻译

获取价格

数据手册

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IS42VS16400E 数据手册

performance.TheꢀsynchronousꢀDRAMsꢀachieveꢀhigh-speedꢀ

data transfer using pipeline architecture. All inputs and

outputs signals refer to the rising edge of the clock input.

IS42VS16400E

1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)

SYNCHRONOUS DYNAMIC RAM

MAY 2009

FEATURES

OVERVIEW

ISSI'sꢀ 64Mbꢀ Synchronousꢀ DRAMꢀ IS42VS16400Eꢀ isꢀ

•ꢀ Clockꢀfrequency:ꢀ133ꢀMHz

organizedꢀasꢀ1,048,576ꢀbitsꢀxꢀ16-bitꢀxꢀ4-bankꢀforꢀimprovedꢀ

•ꢀ Fullyꢀsynchronous;ꢀallꢀsignalsꢀreferencedꢀtoꢀaꢀ

positive clock edge

•ꢀ Internalꢀbankꢀforꢀhidingꢀrowꢀaccess/precharge

•ꢀ Singleꢀ1.8Vꢀpowerꢀsupply

•ꢀ LVCMOSꢀinterface

PIN CONFIGURATIONS

54-Pin TSOP (Type II)

•ꢀ Programmableꢀburstꢀlengthꢀ

–ꢀ(1,ꢀ2,ꢀ4,ꢀ8,ꢀfullꢀpage)

•ꢀ Programmableꢀburstꢀsequence:ꢀ

Sequential/Interleave

VDD

DQ0

VDDQ

DQ1

DQ2

GNDQ

DQ3

DQ4

VDDQ

DQ5

DQ6

GNDQ

DQ7

VDD

LDQM

GND

DQ15

GNDQ

DQ14

DQ13

VDDQ

DQ12

DQ11

GNDQ

DQ10

DQ9

VDDQ

DQ8

GND

•ꢀ Selfꢀrefreshꢀmodes

•ꢀ 4096ꢀrefreshꢀcyclesꢀeveryꢀ64ꢀms

•ꢀ Randomꢀcolumnꢀaddressꢀeveryꢀclockꢀcycle

•ꢀ ProgrammableꢀCASꢀlatencyꢀ(2,ꢀ3ꢀclocks)

•ꢀ Burstꢀread/writeꢀandꢀburstꢀread/singleꢀwriteꢀ

operations capability

UDQM

CLK

CKE

•ꢀ Burstꢀterminationꢀbyꢀburstꢀstopꢀandꢀprechargeꢀ

CAS

RAS

command

BA0

BA1

A10

A11

•ꢀ ByteꢀcontrolledꢀbyꢀLDQMꢀandꢀUDQM

•ꢀ Industrialꢀtemperatureꢀavailability

•ꢀ Packages:

400-milꢀ54-pinꢀTSOPꢀII

54-ballꢀTF-BGAꢀ(8mmꢀxꢀ8mm)

VDD

GND

PIN DESCRIPTIONS

WEꢀ

WriteꢀEnable

A0-A11

Address Input

BA0,ꢀBA1ꢀ

DQ0ꢀtoꢀDQ15ꢀ

BankꢀSelectꢀAddress

DataꢀI/O

LDQMꢀ LowerꢀBye,ꢀInput/OutputꢀMask

UDQMꢀ UpperꢀBye,ꢀInput/OutputꢀMask

CLKꢀ

CKEꢀ

ꢀ

SystemꢀClockꢀInput

ClockꢀEnable

VDDꢀ

Power

GNDꢀ

VDDqꢀ

Ground

Chip Select

PowerꢀSupplyꢀforꢀDQꢀPin

RASꢀ

CAS

ꢀ

RowꢀAddressꢀStrobeꢀCommand

Column Address Strobe Command

GNDqꢀ GroundꢀforꢀDQꢀPin

NCꢀ NoꢀConnection

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device speciﬁcation before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com

Rev. A

05/15/09

12 3 4 5 6 7...58

中文翻译

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与IS42VS16400E相关器件

型号	品牌	获取价格	描述	数据表
IS42VS16400E-75BL	ISSI	获取价格	Random column address every clock cycle
IS42VS16400E-75BLI	ISSI	获取价格	Random column address every clock cycle
IS42VS16400E-75TL	ISSI	获取价格	Random column address every clock cycle
IS42VS16400E-75TLI	ISSI	获取价格	Random column address every clock cycle
IS42VS16800E-10BL	ISSI	获取价格	Synchronous DRAM, 8MX16, 8ns, CMOS, PBGA54, 8 X 8 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA
IS42VS16800E-10BLI	ISSI	获取价格	Synchronous DRAM, 8MX16, 8ns, CMOS, PBGA54, 8 X 8 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA
IS42VS16800E-10TL	ISSI	获取价格	Synchronous DRAM, 8MX16, 8ns, CMOS, PDSO54, 0.400 INCH, ROHS COMPLIANT, TSOP2-54
IS42VS16800E-10TLI	ISSI	获取价格	Synchronous DRAM, 8MX16, 8ns, CMOS, PDSO54, 0.400 INCH, ROHS COMPLIANT, TSOP2-54
IS42VS16800E-75BL	ISSI	获取价格	Synchronous DRAM, 8MX16, 6ns, CMOS, PBGA54, 8 X 8 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA
IS42VS16800E-75TL	ISSI	获取价格	Synchronous DRAM, 8MX16, 6ns, CMOS, PDSO54, 0.400 INCH, ROHS COMPLIANT, TSOP2-54

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