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IS42S32400L-10B PDF预览

IS42S32400L-10B

更新时间: 2024-11-25 04:48:55
品牌 Logo 应用领域
美国芯成 - ISSI 动态存储器
页数 文件大小 规格书
64页 540K
描述
Synchronous DRAM, 4MX32, 7ns, CMOS, PBGA90, BGA-90

IS42S32400L-10B 数据手册

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®
IS42S16800L  
IS42S32400L  
ISSI  
8Meg x16 & 4Meg x 32 (128-MBIT)  
PowerSaver SYNC DYNAMIC RAM  
ADVANCEDINFORMATION  
SEPTEMBER 2002  
OVERVIEW  
FEATURES  
ISSI's 128Mb Synchronous DRAM IS42S16800L is  
organized as 2Meg x16 x 4 banks (8 Meg x16) and the  
IS42S32400Lisorganizedas1Megx32x4banks(4Megx  
32) . The synchronous DRAMs achieve high-speed data  
transfer using pipeline architecture. All inputs and outputs  
signals refer to the rising edge of the clock input.  
• Clock frequency: 143, 100, MHz  
• Fully synchronous; all signals referenced to a  
positive clock edge  
• Internal bank for hiding row access/precharge  
• Power supply  
VDD = 2.5V/ +/-10%  
VDDq= 1.8V (2.5V tolerant)  
• LVTTL interface  
Package:  
54-Ball FBGA for x16  
54 Pin TSOPII for x16  
90-Ball FBGA for x32  
86-Pin TSOPII for x32  
• Programmable burst length  
– (1, 2, 4, 8, full page)  
• Programmable burst sequence:  
Sequential/Interleave  
• Extended Mode Register  
• Programmable Power Reduction Feature by  
partial array activation during Self-Refresh  
KEY TIMING PARAMETERS  
• Auto Refresh (CBR)  
• Temp. Compensated Self Refresh.  
• Self Refresh with programmable refresh periods  
• 4096 refresh cycles every 64 ms  
Parameter  
-7  
-10 Unit  
Clk Cycle Time  
CAS Latency = 3  
CAS Latency = 2  
7
10  
10  
10  
ns  
ns  
• Random column address every clock cycle  
• Programmable CAS latency (2, 3 clocks)  
Clk Frequency  
CAS Latency = 3  
CAS Latency = 2  
143  
100  
100  
100  
Mhz  
Mhz  
• Burst read/write and burst read/single write  
operations capability  
Access Time from Clock  
CAS Latency = 3  
5.4  
6
7
9
ns  
ns  
• Burst termination by burst stop and precharge  
command  
CAS Latency = 2  
Row to Column Delay Time (tRCD)  
Row Precharge Tim (tRP)  
15  
15  
18  
18  
ns  
ns  
• Industrial Temperature Availability  
• Bare and Known Good Die  
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any  
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are  
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
Rev. 00B  
1
09/24/02  

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