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IS42S16160-75ETL PDF预览

IS42S16160-75ETL

更新时间: 2024-02-13 08:07:09
品牌 Logo 应用领域
美国芯成 - ISSI 时钟动态存储器光电二极管内存集成电路
页数 文件大小 规格书
60页 888K
描述
Synchronous DRAM, 16MX16, 5.5ns, CMOS, PDSO54,

IS42S16160-75ETL 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSOP, TSOP54,.46,32Reach Compliance Code:compliant
风险等级:5.75最长访问时间:5.5 ns
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
交错的突发长度:1,2,4,8JESD-30 代码:R-PDSO-G54
内存密度:268435456 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:16端子数量:54
字数:16777216 words字数代码:16000000
最高工作温度:70 °C最低工作温度:
组织:16MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP
封装等效代码:TSOP54,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE电源:3.3 V
认证状态:Not Qualified刷新周期:8192
连续突发长度:1,2,4,8,FP最大待机电流:0.003 A
子类别:DRAMs最大压摆率:0.18 mA
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUALBase Number Matches:1

IS42S16160-75ETL 数据手册

 浏览型号IS42S16160-75ETL的Datasheet PDF文件第2页浏览型号IS42S16160-75ETL的Datasheet PDF文件第3页浏览型号IS42S16160-75ETL的Datasheet PDF文件第4页浏览型号IS42S16160-75ETL的Datasheet PDF文件第5页浏览型号IS42S16160-75ETL的Datasheet PDF文件第6页浏览型号IS42S16160-75ETL的Datasheet PDF文件第7页 
IS42S16160  
16Meg x16  
256-MBIT SYNCHRONOUS DRAM  
SEPTEMBER 2009  
FEATURES  
OVERVIEW  
ISSI'sꢀ256MbꢀSynchronousꢀDRAMꢀꢀachievesꢀhigh-speedꢀ  
data transfer using pipeline architecture. All inputs and  
outputs signals refer to the rising edge of the clock input.  
Theꢀ256MbꢀSDRAMꢀisꢀorganizedꢀasꢀfollows.ꢀ  
•ꢀ Clockꢀfrequency:ꢀ166,ꢀ143,ꢀ133ꢀꢀMHz  
•ꢀ Fullyꢀsynchronous;ꢀallꢀsignalsꢀreferencedꢀtoꢀaꢀ  
positive clock edge  
•ꢀ Internalꢀbankꢀforꢀhidingꢀrowꢀaccess/precharge  
•ꢀ Powerꢀsupply  
Vd d  
Vd d q  
IS42S16160ꢀ  
ꢀ3.3Vꢀ 3.3Vꢀꢀ  
IS42S16160ꢀ  
•ꢀ LVTTLꢀinterface  
4Mꢀx16x4ꢀBanksꢀ  
54-pinꢀTSOPII  
54-ballꢀTF-BGAꢀ ꢀ  
•ꢀ Programmableꢀburstꢀlengthꢀ  
–ꢀ(1,ꢀ2,ꢀ4,ꢀ8,ꢀfullꢀpage)  
•ꢀ Programmableꢀburstꢀsequence:ꢀ  
Sequential/Interleaveꢀ  
•ꢀ AutoꢀRefreshꢀ(CBR)  
•ꢀ SelfꢀRefresh  
•ꢀ 8Kꢀrefreshꢀcyclesꢀeveryꢀ64ꢀms  
•ꢀ Randomꢀcolumnꢀaddressꢀeveryꢀclockꢀcycle  
•ꢀ ProgrammableꢀCASꢀlatencyꢀ(2,ꢀ3ꢀclocks)  
KEY TIMING PARAMETERS  
Parameter  
-6  
-7  
-75E Unit  
•ꢀ Burstꢀread/writeꢀandꢀburstꢀread/singleꢀwriteꢀ  
ClkꢀCycleꢀTimeꢀ  
CASꢀLatencyꢀ=ꢀ3ꢀ  
CASꢀLatencyꢀ=ꢀ2ꢀ  
ꢀꢀ  
6ꢀ  
10ꢀ  
7ꢀ  
10ꢀ  
operations capability  
–ꢀ  
7.5ꢀ  
nsꢀ  
ns  
•ꢀ Burstꢀterminationꢀbyꢀburstꢀstopꢀandꢀprechargeꢀ  
ClkꢀFrequencyꢀ  
ꢀꢀ  
command  
CASꢀLatencyꢀ=ꢀ3ꢀ  
CASꢀLatencyꢀ=ꢀ2ꢀ  
166ꢀ  
100ꢀ  
143ꢀ  
100ꢀ  
–ꢀ  
133ꢀ  
Mhzꢀ  
Mhz  
•ꢀ AvailableꢀinꢀIndustrialꢀꢀTemperature  
•ꢀ Availableꢀinꢀ54-pinꢀTSOP-IIꢀandꢀ54-ballꢀTF-BGA  
•ꢀ AvailableꢀinꢀLead-free  
AccessꢀTimeꢀꢀfromꢀClockꢀ  
CASꢀLatencyꢀ=ꢀ3ꢀ  
CASꢀLatencyꢀ=ꢀ2ꢀ  
5.4ꢀ  
8ꢀ  
5.4ꢀ  
8ꢀ  
–ꢀ  
5.5ꢀ  
nsꢀ  
ns  
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with-  
out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain  
the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com  
1
Rev. C  
09/15/09  

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