IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D
PiN FUNcTiONS
Symbol
Type
Funꢁtꢀon (in detaꢀl)
ꢀ
A0-A12ꢀ
ꢀ
InputꢀPin
ꢀ
AddressꢀInputs:ꢀA0-A12ꢀareꢀsampledꢀduringꢀtheꢀACTIVEꢀcommandꢀ(row-addressꢀ
A0-A12)ꢀandꢀREAD/WRITEꢀcommandꢀ(columnꢀaddressꢀA0-A9,ꢀA11ꢀ(x8);ꢀA0-A9ꢀ
(x16);ꢀA0-A8ꢀ(x32);ꢀwithꢀA10ꢀdefiningꢀautoꢀprecharge)ꢀtoꢀselectꢀoneꢀlocationꢀoutꢀofꢀ
theꢀmemoryꢀarrayꢀinꢀtheꢀrespectiveꢀbank.ꢀA10ꢀisꢀsampledꢀduringꢀaꢀPRECHARGEꢀ
commandꢀtoꢀdetermineꢀifꢀallꢀbanksꢀareꢀtoꢀbeꢀprechargedꢀ(A10ꢀHIGH)ꢀorꢀbankꢀ
selectedꢀbyꢀBA0,ꢀBA1ꢀ(LOW).ꢀTheꢀaddressꢀinputsꢀalsoꢀprovideꢀtheꢀop-codeꢀduringꢀaꢀ
LOADꢀMODEꢀREGISTERꢀcommand.
ꢀ
ꢀ
ꢀ
BA0,ꢀBA1
ꢀ
ꢀ
ꢀ
ꢀ
InputꢀPin
InputꢀPin
InputꢀPin
ꢀ
ꢀ
ꢀ
BankꢀSelectꢀAddress:ꢀBA0ꢀandꢀBA1ꢀdefinesꢀwhichꢀbankꢀtheꢀACTIVE,ꢀREAD,ꢀWRITEꢀ
orꢀPRECHARGEꢀcommandꢀisꢀbeingꢀapplied.
CASꢀ
CAS,ꢀinꢀconjunctionꢀwithꢀtheꢀRASꢀandꢀꢀWE,ꢀformsꢀtheꢀdeviceꢀcommand.ꢀSeeꢀtheꢀ
"CommandꢀTruthꢀTable"ꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ
CKEꢀ
TheꢀCKEꢀinputꢀdeterminesꢀwhetherꢀtheꢀCLKꢀinputꢀisꢀenabled.ꢀTheꢀnextꢀrisingꢀedgeꢀ
ofꢀtheꢀCLKꢀsignalꢀwillꢀbeꢀvalidꢀwhenꢀisꢀCKEꢀHIGHꢀandꢀinvalidꢀwhenꢀLOW.ꢀWhenꢀCKEꢀ
isꢀLOW,ꢀtheꢀdeviceꢀwillꢀbeꢀinꢀeitherꢀpower-downꢀmode,ꢀclockꢀsuspendꢀmode,ꢀorꢀselfꢀ
refreshꢀmode.ꢀCKEꢀisꢀanꢀasynchronousꢀinput.
ꢀ
ꢀ
CLKꢀ
ꢀ
ꢀ
InputꢀPin
InputꢀPin
ꢀ
ꢀ
CLKꢀisꢀtheꢀmasterꢀclockꢀinputꢀforꢀthisꢀdevice.ꢀExceptꢀforꢀCKE,ꢀallꢀinputsꢀtoꢀthisꢀdeviceꢀ
areꢀacquiredꢀinꢀsynchronizationꢀwithꢀtheꢀrisingꢀedgeꢀofꢀthisꢀpin.
CSꢀ
TheꢀCSꢀinputꢀdeterminesꢀwhetherꢀcommandꢀinputꢀisꢀenabledꢀwithinꢀtheꢀdevice.ꢀ
CommandꢀinputꢀisꢀenabledꢀwhenꢀCSꢀisꢀLOW,ꢀandꢀdisabledꢀwithꢀCSꢀisꢀHIGH.ꢀTheꢀ
deviceꢀremainsꢀinꢀtheꢀpreviousꢀstateꢀwhenꢀCSꢀisꢀHIGH.
ꢀ
DQM:ꢀx8ꢀ
ꢀ
ꢀ
ꢀ
InputꢀPin
ꢀ
DQxꢀpinsꢀcontrolꢀtheꢀbytesꢀofꢀtheꢀI/Oꢀbuffers.ꢀForꢀexampleꢀwithꢀx16,ꢀinꢀreadꢀmode,
DQMLꢀandꢀDQMHꢀcontrolꢀtheꢀoutputꢀbuffer.ꢀWhenꢀDQMLꢀorꢀDQMHꢀisꢀLOW,ꢀthe
DQML,ꢀDQMH:ꢀx16ꢀ
DQM0-DQM3:ꢀx32ꢀ
ꢀ
ꢀ
correspondingꢀbufferꢀbyteꢀisꢀenabled,ꢀandꢀwhenꢀHIGH,ꢀdisabled.ꢀTheꢀoutputsꢀgoꢀtoꢀ
theꢀHIGHꢀimpedanceꢀstateꢀwhenꢀDQML/DQMHꢀisꢀHIGH.ꢀThisꢀfunctionꢀcorrespondsꢀ
toꢀOEꢀinꢀconventionalꢀDRAMs.ꢀInꢀwriteꢀmode,ꢀDQMLꢀandꢀDQMHꢀcontrolꢀtheꢀinputꢀ
buffer.ꢀWhenꢀDQMLꢀorꢀDQMHꢀisꢀLOW,ꢀtheꢀcorrespondingꢀbufferꢀbyteꢀisꢀenabled,ꢀ
andꢀdataꢀcanꢀbeꢀwrittenꢀtoꢀtheꢀdevice.ꢀWhenꢀDQMLꢀorꢀDQMHꢀisꢀHIGH,ꢀinputꢀdataꢀisꢀ
maskedꢀandꢀcannotꢀbeꢀwrittenꢀtoꢀtheꢀdevice.
ꢀ
ꢀ
DQ0-DQ7:ꢀx8ꢀ
DQ0-DQ15:ꢀx16ꢀ
ꢀ Input/Outputꢀ
DataꢀonꢀtheꢀDataꢀBusꢀisꢀlatchedꢀonꢀDQꢀpinsꢀduringꢀWriteꢀcommands,ꢀandꢀbufferedꢀfor
outputꢀafterꢀReadꢀcommands.
ꢀ
ꢀ
ꢀ
ꢀ
DQ0-DQ31:ꢀx32
RASꢀ
ꢀ
ꢀ
InputꢀPin
ꢀ
RAS,ꢀinꢀconjunctionꢀwithꢀCASꢀandꢀWE,ꢀformsꢀtheꢀdeviceꢀcommand.ꢀSeeꢀtheꢀ"Com-
mandꢀTruthꢀTable"ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.
ꢀ
WEꢀ
ꢀInputꢀPin
ꢀ
WE,ꢀinꢀconjunctionꢀwithꢀRASꢀandꢀCAS,ꢀformsꢀtheꢀdeviceꢀcommand.ꢀSeeꢀtheꢀ"Com-
mandꢀTruthꢀTable"ꢀitemꢀforꢀdetailsꢀonꢀdeviceꢀcommands.ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Vddqꢀ
Vddꢀ
PowerꢀSupplyꢀPin
PowerꢀSupplyꢀPin
PowerꢀSupplyꢀPin
PowerꢀSupplyꢀPin
ꢀ
ꢀ
ꢀ
ꢀ
Vddq isꢀtheꢀoutputꢀbufferꢀpowerꢀsupply.
Vddꢀisꢀtheꢀdeviceꢀinternalꢀpowerꢀsupply.
Vssqꢀisꢀtheꢀoutputꢀbufferꢀground.
Vssqꢀ
Vssꢀ
Vssꢀisꢀtheꢀdeviceꢀinternalꢀground.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
7
Rev.ꢀ00B
06/09/2011
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