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IS23SC1604-PI PDF预览

IS23SC1604-PI

更新时间: 2024-02-02 04:44:15
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
18页 78K
描述
16-KBIT SECURED SERIAL EEPROM

IS23SC1604-PI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.88
Is Samacsys:N其他特性:1000000 ERASE/WRITE CYCLES; 10 YEARS DATA RETENTION
最大时钟频率 (fCLK):0.3 MHz数据保留时间-最小值:10
JESD-30 代码:R-PDIP-T8JESD-609代码:e0
长度:9.3218 mm内存密度:16384 bit
内存集成电路类型:EEPROM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:8字数:2048 words
字数代码:2000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:2KX8封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:SERIAL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:4.572 mm串行总线类型:3-WIRE
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

IS23SC1604-PI 数据手册

 浏览型号IS23SC1604-PI的Datasheet PDF文件第2页浏览型号IS23SC1604-PI的Datasheet PDF文件第3页浏览型号IS23SC1604-PI的Datasheet PDF文件第4页浏览型号IS23SC1604-PI的Datasheet PDF文件第6页浏览型号IS23SC1604-PI的Datasheet PDF文件第7页浏览型号IS23SC1604-PI的Datasheet PDF文件第8页 
®
IS23SC1604  
ISSI  
Device Operations(1)  
Operation  
FUS  
PGM  
RST  
CLK  
Description  
The address counter is reset to zero and the  
Reset  
X
X
0
first bit of the memory is output after the falling  
edge of RST.  
INC/Read  
INC/CMP  
X
X
0
0
0
0
The address counter is incremented and the first  
bit is output after the falling edge of the clock if  
read access to the bit location is enabled.  
Compare the input bit with the internal bit of the  
memory (for Security/Erase Key codes validation).  
The address counter is incremented on the falling  
edge of CLK.The input bit is latched into the device  
at the rising edge of CLK and the bit comparison  
is done on the next falling edge of CLK.  
Erase/Write  
X
1
0
For write operation (write a ‘0’ to the current  
address), a ‘0’ is placed on I/O before the rising  
edge of CLK. For erase byte operation (write FFH  
to the byte that contains the current bit), a ‘1’ is  
placed on I/O before the rising edge of CLK. CLK  
must stay HIGH for 5 ms during memory programming.  
Verify  
X
0
0
0
0
1
The new content of the current address will be  
output after the falling edge of CLK for verification.  
Standby  
X
The device is placed into standby mode. In this  
mode, the address counter will not be incremented  
with clock pulse when RST is HIGH.  
Note:  
1. X = Don’t Care.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
ADVANCE INFORMATION Rev. 00E  
5
04/10/03  

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