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IS23SC1604-PI PDF预览

IS23SC1604-PI

更新时间： 2024-01-24 14:52:03
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
18页 78K
描述
16-KBIT SECURED SERIAL EEPROM

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中文翻译

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IS23SC1604-PI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.51风险等级：5.88
Is Samacsys：N其他特性：1000000 ERASE/WRITE CYCLES; 10 YEARS DATA RETENTION
最大时钟频率 (fCLK)：0.3 MHz数据保留时间-最小值：10
JESD-30 代码：R-PDIP-T8JESD-609代码：e0
长度：9.3218 mm内存密度：16384 bit
内存集成电路类型：EEPROM内存宽度：8
湿度敏感等级：3功能数量：1
端子数量：8字数：2048 words
字数代码：2000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：2KX8封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE并行/串行：SERIAL
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：4.572 mm串行总线类型：3-WIRE
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.62 mm
Base Number Matches：1

IS23SC1604-PI 数据手册

 浏览型号IS23SC1604-PI的Datasheet PDF文件第10页浏览型号IS23SC1604-PI的Datasheet PDF文件第11页浏览型号IS23SC1604-PI的Datasheet PDF文件第12页浏览型号IS23SC1604-PI的Datasheet PDF文件第14页浏览型号IS23SC1604-PI的Datasheet PDF文件第15页浏览型号IS23SC1604-PI的Datasheet PDF文件第16页 
®
IS23SC1604  
ISSI  
Security/Erase Key Code Validation  
A.  
Reset  
B.  
Read  
C.  
D.  
Read  
E.  
Write  
F.  
Verify  
H.  
Verify  
G.  
Erase  
I.  
Read  
Operation  
Address  
Compare  
0
1
2
RST  
T
CHP  
T
CHP  
CLK  
PGM  
0
0
0
0
0
1
1
In  
1
I/O  
(mode)  
Out  
Out  
In  
In  
Out  
In  
Out  
Out  
In  
Out  
Out  
Out Out  
Out Out  
Out  
In  
Security/Erase  
Code Flag  
Security/Erase  
Code Zone  
(16-bits)  
Security/Erase Code  
Attempts Counter  
FZ, IZ, É  
SECURITY/ERASE KEY CODE VALIDATION OPERATION  
(For SC, SC1, EZ1, EZ2, EZ3, and EZ4 validation)  
A. Reset the address counter to zero.  
H. If the comparison flag were successfully set to ‘1’, the  
erasure of the attempt counter would be allowed and  
the device would output a ‘1’ on I/O after the erase op-  
eration. Otherwise, the erasure of the attempt counter  
would be blocked and a‘0’would be output on I/O. (The  
content of the attempt counter remains unchanged.)  
B. Send required number of clock pulses to increment the  
address counter to security/erase key code location.  
C. Input the security/erase key code bit by bit for code vali-  
dation.  
D. After security/erase key code entry, look for the first logic  
‘1’bit in security/erase key code attempts counter.If the  
‘1’ bit is found, do not increment the address.  
I. On the following edge of the clock, the address counter  
is incremented and the state of the next bit is output on  
I/O.  
Notes:  
E. Write a ‘0’ over the ‘1’ bit in security/erase key code at-  
tempts counter at the current bit location.  
1. The address counter does not increment from steps E to H.  
2. After eight consecutive failed attempts to validate the secu-  
rity/erase key code, the corresponding flag will be locked at ‘0’  
permanently.  
F. The chip outputs a ‘0’ after programming is done.  
G.If the security/erase key code validation was success-  
ful, the corresponding comparison flag will be set to ‘1’  
on the rising edge of PGM and the security/erase key  
code attempts counter should be erased to reactivate  
the eight allowable attempts. (The validation operation  
can be aborted by setting CLK HIGH when PGM is still  
LOW.)  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
ADVANCE INFORMATION Rev. 00E  
13  
04/10/03  
1...10111213141516...18

中文翻译

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