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IPSH4N03LAG PDF预览

IPSH4N03LAG

更新时间: 2024-01-28 19:57:27
品牌 Logo 应用领域
英飞凌 - INFINEON 晶体晶体管功率场效应晶体管开关脉冲
页数 文件大小 规格书
9页 305K
描述
OPTIMOS 2 POWER - TRANSISTOR

IPSH4N03LAG 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TO-251包装说明:IN-LINE, R-PSIP-T3
针数:3Reach Compliance Code:compliant
ECCN代码:EAR99风险等级:5.82
Is Samacsys:N其他特性:LOGIC LEVEL COMPATIBLE
雪崩能效等级(Eas):150 mJ配置:SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压:25 V最大漏极电流 (Abs) (ID):90 A
最大漏极电流 (ID):90 A最大漏源导通电阻:0.0044 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJEDEC-95代码:TO-251
JESD-30 代码:R-PSIP-T3JESD-609代码:e3
元件数量:1端子数量:3
工作模式:ENHANCEMENT MODE最高工作温度:175 °C
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
极性/信道类型:N-CHANNEL最大功率耗散 (Abs):94 W
最大脉冲漏极电流 (IDM):360 A认证状态:Not Qualified
子类别:FET General Purpose Power表面贴装:NO
端子面层:MATTE TIN端子形式:THROUGH-HOLE
端子位置:SINGLE处于峰值回流温度下的最长时间:NOT SPECIFIED
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

IPSH4N03LAG 数据手册

 浏览型号IPSH4N03LAG的Datasheet PDF文件第1页浏览型号IPSH4N03LAG的Datasheet PDF文件第3页浏览型号IPSH4N03LAG的Datasheet PDF文件第4页浏览型号IPSH4N03LAG的Datasheet PDF文件第5页浏览型号IPSH4N03LAG的Datasheet PDF文件第6页浏览型号IPSH4N03LAG的Datasheet PDF文件第7页 
IPDH4N03LA G  
Values  
IPSH4N03LA G  
Parameter  
Symbol Conditions  
Unit  
min.  
typ.  
max.  
Thermal characteristics  
R thJC  
Thermal resistance, junction - case  
SMD version, device on PCB  
-
-
-
-
-
-
1.6  
75  
50  
K/W  
R thJA  
minimal footprint  
6 cm2 cooling area5)  
Electrical characteristics, at T j=25 °C, unless otherwise specified  
Static characteristics  
V (BR)DSS  
V GS(th)  
V
V
GS=0 V, I D=1 mA  
DS=V GS, I D=40 µA  
Drain-source breakdown voltage  
Gate threshold voltage  
25  
-
-
V
1.2  
1.6  
2
V
DS=25 V, V GS=0 V,  
I DSS  
Zero gate voltage drain current  
-
-
0.1  
10  
1
µA  
T j=25 °C  
V
DS=25 V, V GS=0 V,  
100  
T j=125 °C  
I GSS  
V
V
GS=20 V, V DS=0 V  
GS=4.5 V, I D=50 A  
Gate-source leakage current  
-
-
10  
100 nA  
R DS(on)  
Drain-source on-state resistance  
6.1  
7.6  
7.4  
4.4  
4.2  
-
mΩ  
V
GS=4.5 V, I D=50 A,  
-
-
5.9  
3.7  
3.5  
1.3  
90  
SMD version  
V
GS=10 V, I D=60 A  
V
GS=10 V, I D=60 A,  
-
SMD version  
R G  
g fs  
Gate resistance  
-
|V DS|>2|I D|R DS(on)max  
I D=60 A  
,
Transconductance  
45  
-
S
1) J-STD20 and JESD22  
1) Current is limited by bondwire; with anR thJC=1.6 K/W the chip is able to carry 109 A.  
3) See figure 3  
4) T j,max=150 °C and duty cycle D <0.25 for V GS<-5 V  
5) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm (one layer, 70 µm thick) copper area for drain  
connection. PCB is vertical in still air.  
2
Rev. 0.92 - target data sheet  
page 2  
2004-10-27  

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