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IMP5111CPWPT PDF预览

IMP5111CPWPT

更新时间: 2024-10-28 04:23:03
品牌 Logo 应用领域
IMP /
页数 文件大小 规格书
6页 159K
描述
9--Liine SCSII Termiinattor - 35MHz Channell Bandwiidtth

IMP5111CPWPT 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:PLASTIC, TSSOP-24针数:24
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
Is Samacsys:N差分输出:NO
接口集成电路类型:SCSI BUS TERMINATORJESD-30 代码:R-PDSO-G24
功能数量:1信号线数量:9
端子数量:24最高工作温度:125 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
认证状态:Not Qualified最大压摆率:225 mA
最大供电电压:5.5 V最小供电电压:3.3 V
标称供电电压:4.75 V表面贴装:YES
温度等级:OTHER端子形式:GULL WING
端子位置:DUALBase Number Matches:1

IMP5111CPWPT 数据手册

 浏览型号IMP5111CPWPT的Datasheet PDF文件第2页浏览型号IMP5111CPWPT的Datasheet PDF文件第3页浏览型号IMP5111CPWPT的Datasheet PDF文件第4页浏览型号IMP5111CPWPT的Datasheet PDF文件第5页浏览型号IMP5111CPWPT的Datasheet PDF文件第6页 
IMP5111/5112  
DATA  
C
OMMUNICATIONS  
Key Features  
9-Line SCSI Terminator  
Ultra-Fast response for Fast-20 SCSI applications  
35MHz channel bandwidth  
– 35MHz Channel Bandwidth  
The 9-channel IMP5111/ 5112 SCSI terminator is part of IMP's family  
of high-performance SCSI terminators that deliver true UltraSCSI per-  
formance. The BiCMOS design offers superior performance over first  
generation linear regulator/ resistor based terminators.  
3.3V operation  
Less than 3pF output capacitance  
Sleep-mode current less than 275µA  
Thermally self limiting  
No external compensation capacitors  
Implements 8-bit or 16-bit (wide) applications  
Compatible with active negation drivers  
(60mA/ channel)  
Compatible with passive and active terminations  
Approved for use with SCSI 1, 2, 3 and UltraSCSI  
Hot swap compatible  
Pin-for-pin compatible with LX5211 and  
UC5606 (IMP5111)  
IMP's new architecture employs high-speed adaptive elements for each  
channel, thereby providing the fastest response possible - typically  
35MHz, which is 100 times faster than the older linear regulator termi-  
nator approach. The bandwidth of terminators based on the older  
regulator/ resistor terminator architecture is limited to 500kHz since a  
large output stabilization capacitor is required. The IMP architecture  
eliminates the external output compensation capacitor and the need  
for transient output capacitors while maintaining pin compatibility  
with first generation designs. Reduced component count is inherent  
with the IMP5111/ 5112.  
The IMP5111/ 5112 architecture tolerates marginal system designs. A key  
improvement offered by the IMP5111/ 5112 lies in its ability to insure  
reliable, error-free communications even in systems which do not adhere  
to recommended SCSI hardware design guidelines, such as improper  
cable lengths and impedance. Frequently, this situation is not controlled  
by the peripheral or host designer.  
Pin-for-pin compatible with LX5212 and  
UC5603/ 5613/ 5614 (IMP5112)  
For portable and configurable peripherals, the IMP5111/ 5112 can be  
placed in a sleep mode with a disconnect signal. Quiescent current is less  
than 275µA when disabled. When disabled, the outputs are in a high  
impedance state with output capacitance less than 3pF.  
Block Diagrams  
Term Power  
24mA Current  
Limiting Circuit  
DATA OUTPUT  
PIN DB (0)  
Thermal  
Limiting  
Circuit  
Current  
Biasing  
Circuit  
2.85V  
DISCONNECT (IMP5111)  
DISCONNECT (IMP5112)  
+
1 of 9 Channels  
1.4V  
5111/5112_01.eps  
Daily Silver IMP  
www.ds-imp.com.cn  
1

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