Datasheet > IDT7M1001

IDT7M1001

更新时间： 2022-11-26 03:00:57

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
11页	175K
描述
128K x 8 64K x 8 CMOS DUAL-PORT STATIC RAM MODULE

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IDT7M1001 数据手册

IDT7M1001/1003

128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (R/ CONTROLLED TIMING)^(1,3,5,8)

ADDRESS

(9)

OHZ

(6)

(7)

tWR

(2)

R/W

(9)

WHZ

(4)

DATA OUT

DATA IN

(4)

t DH

DATA VALID

2804 drw 08

NOTES:

1. R/W is HIGH for Read Cycles

2. Device is continuously enabled. CS = LOW. UB or LB = LOW. This waveform cannot be used for semaphore reads.

3. Addresses valid prior to or coincident with CS transition low.

4. OE = LOW.

5. To access RAM, CS = LOW, UB or LB = LOW, SEM = H. To access semaphore, CS = HIGH and SEM = LOW.

6. Timing depends on which enable signal is asserted last.

7. Timing depends on which enable signal is de-asserted first.

8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to

be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse width

be as short as the specified tWP.

9. This parameter is guaranteed by design but not tested.

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (

CONTROLLED TIMING)^(1,3,5,8)

t WC

ADDRESS

t AW

(6)

t AS

(7)

(2)

tWR

R/W

t DW

t DH

DATA IN

DATA VALID

2804 drw 09

NOTES:

1. R/W must be HIGH during all address transitions.

2. A write occurs during the overlap (tWP) of a LOW UB or LB and a LOW CS and a LOW R/W for memory array writing cycle.

3. tWR is measured from the earlier of CS or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CS or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.

6. Timing depends on which enable signal is asserted last.

7. Timing depends on which enable signal is de-asserted first.

8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data

to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can

be as short as the specified tWP.

9. This parameter is guaranteed by design but not tested.

7.5

1...4 5 678 9 10 11

下载PDF

与IDT7M1001相关器件

型号	品牌	描述	获取价格	数据表
IDT7M1001S25C	ETC	x8 Dual-Port SRAM Module	获取价格
IDT7M1001S30C	ETC	x8 Dual-Port SRAM Module	获取价格
IDT7M1001S30CB	ETC	x8 Dual-Port SRAM Module	获取价格
IDT7M1001S35C	IDT	128K x 8 64K x 8 CMOS DUAL-PORT STATIC RAM MODULE	获取价格
IDT7M1001S35CB	IDT	128K x 8 64K x 8 CMOS DUAL-PORT STATIC RAM MODULE	获取价格
IDT7M1001S40C	IDT	128K x 8 64K x 8 CMOS DUAL-PORT STATIC RAM MODULE	获取价格