Datasheet > IDT7M1001

IDT7M1001

更新时间： 2022-11-26 03:00:57

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
11页	175K
描述
128K x 8 64K x 8 CMOS DUAL-PORT STATIC RAM MODULE

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数据手册

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IDT7M1001 数据手册

IDT7M1001/1003

128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO. 1 (EITHER SIDE)^(1,2,4)

tRC

ADDRESS

t_OH

t OH

DATA OUT

DATA VALID

PREVIOUS DATA VALID

2804 drw 06

TIMING WAVEFORM OF READ CYCLE NO. 2 (EITHER SIDE)^(1,3,5)

tACS

(6)

tCHZ

t OE

(6)

tOHZ

(6)

tOLZ

DATA _OUT

DATA VALID

(6)

CLZ

(6)

tPU

(6)

tPD

ICC

CURRENT

50%

ISB

2804 drw 07

NOTES:

1. R/W is HIGH for Read Cycles

2. Device is continuously enabled. CS = LOW. This waveform cannot be used for semaphore reads.

3. Addresses valid prior to or coincident with CS transition LOW.

4. OE = LOW.

5. To access RAM, CS = LOW, SEM = H. To access semaphore, CS = HIGH and SEM = LOW.

6. This parameter is guaranteed by design but not tested.

7.5

1...3 4 567 8 9...11

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