IDT79R4700
This data sheet provides an overview of the R4700’s CPU features
and architecture. A more detailed description of this processor is
provided in the IDT79R4700 RISC Processor Hardware User’s Manual,
available from Integrated Device Technology (IDT). Information on
development support, applications notes and complementary products
is available on the IDT Web site www.idt.com or through your local IDT
sales representative.
resource dependencies are made transparent to the programmer,
insuring transportability among implementations of the MIPS instruction
set architecture.
The MIPS integer unit implements a load/store architecture with
single cycle ALU operations (logical, shift, add, sub) and an autono-
mous multiply/divide unit. Register resources include:
◆
32 general-purpose orthogonal integer registers
Note: Throughout this data sheet and any other IDT materials for this
device, the R4700 indicates a 5V part; RV4700 designates a reduced
voltage (3V) part; and the RC4700 reflects either.
◆
HI/LO result registers, for the integer multiply/divide unit
◆
Program counter
Also, the on-chip floating-point co-processor adds 32 floating-point
registers and a floating-point control/status register.
Count
9*
Compare
11*
Register File
PageMask
5*
EntryLo0
2*
Status
Cause
The R4700 has 32 general-purpose registers (shown in Figure 2).
These registers are used for scalar integer operations and address
calculation. The register file consists of two read ports and one write
port and is fully bypassed to minimize operation latency in the pipeline.
EntryHi
10*
EntryLo1
33**
12*
13*
47
EPC
14*
ErrorEPC
30*
Index
0*
Context
4*
XContext
20*
General Purpose Registers
Multiply/Divide Registers
TLB
Random
1*
63
0
BadVAddr
8*
LLAddr
17*
0
r1
r2
•
63
63
0
0
Wired
6*
PRId
Config
HI
(entries protected
15*
16*
from TLBWR)
0
TagHi
29*
TagLo
28*
LO
* Register number
•
ECC
26*
CacheErr
27*
•
Program Counter
•
63
0
r29
r30
r31
PC
Figure 1 The RC4700 CPO Registers
Hardware Overview
Figure 2 R4700 CPU Registers
The RC4700 processor family brings a high-level of integration
designed for high-performance computing. The R4700’s key elements
are briefly described below. A more detailed explanation of each
subsystem is available in the user’s manual.
ALU
The RC4700 ALU consists of the integer adder and logic unit. The
adder performs address calculations in addition to arithmetic operations,
and the logic unit performs all logical and shift operations. Each of these
units is highly optimized and can perform an operation in a single pipe-
line cycle.
Pipeline
The RC4700 uses a simple 5-stage pipeline, similar to the pipeline
structure implemented in the IDT79R32364. This pipeline’s simplicity
allows the RC4700 to be lower cost and lower power than super-scalar
or super-pipelined processors. The pipeline stages are shown in Figure
3 on page 3.
Integer Multiply/Divide
To perform integer multiply and divide operations, the RC4700 uses
the floating-point unit. The results of the operation are placed in the HI
and LO registers. The values can then be transferred to the general
purpose register file using the MFHI/MFLO instructions. To prevent the
Integer Execution Engine
The R4700 implements the MIPS-III Instruction Set architecture and
is upwardly compatible with applications that run on earlier generation
parts.
Implementation of the MIPS-III architecture results in 64-bit opera-
tions, better code density, greater multi-processing support, improved
performance for commonly used code sequences in operating system
kernels and faster execution of floating-point intensive applications. All
2 of 25
April 10, 2001
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