5秒后页面跳转
IDT74SSTVN16859CNLG8 PDF预览

IDT74SSTVN16859CNLG8

更新时间: 2024-11-11 14:30:03
品牌 Logo 应用领域
艾迪悌 - IDT 逻辑集成电路触发器电视
页数 文件大小 规格书
7页 77K
描述
D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 13-Bit, True Output, PQCC56, GREEN, PLASTIC, VFQFN-56

IDT74SSTVN16859CNLG8 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:QFN包装说明:GREEN, PLASTIC, VFQFN-56
针数:56Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.16
Is Samacsys:N系列:SSTV
JESD-30 代码:S-PQCC-N56JESD-609代码:e3
长度:8 mm逻辑集成电路类型:D FLIP-FLOP
位数:13功能数量:1
端子数量:56最高工作温度:70 °C
最低工作温度:输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260传播延迟(tpd):2.2 ns
认证状态:Not Qualified座面最大高度:1 mm
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
触发器类型:POSITIVE EDGE宽度:8 mm
最小 fmax:220 MHzBase Number Matches:1

IDT74SSTVN16859CNLG8 数据手册

 浏览型号IDT74SSTVN16859CNLG8的Datasheet PDF文件第2页浏览型号IDT74SSTVN16859CNLG8的Datasheet PDF文件第3页浏览型号IDT74SSTVN16859CNLG8的Datasheet PDF文件第4页浏览型号IDT74SSTVN16859CNLG8的Datasheet PDF文件第5页浏览型号IDT74SSTVN16859CNLG8的Datasheet PDF文件第6页浏览型号IDT74SSTVN16859CNLG8的Datasheet PDF文件第7页 
IDT74SSTVN16859C  
13-BIT TO 26-BIT REGISTERED  
BUFFER WITH SSTL I/O  
FEATURES:  
DESCRIPTION:  
• 1:2 registered output buffer  
The SSTVN16859C is a 13-bit to 26-bit registered buffer designed for  
2.3V-2.7VVDD forPC1600-PC2700and2.5V-2.7VVDD forPC3200, and  
supports low standby operation. All data inputs and outputs are SSTL_2  
level compatible with JEDEC standard for SSTL_2.  
• 2.3V to 2.7V operation for PC1600, PC2100, and PC2700  
• 2.5V to 2.7V operation for PC3200  
• SSTL_2 Class I style data inputs/outputs  
• Differential CLK input  
RESET control compatible with LVCMOS levels  
• Latch-up performance exceeds 100mA  
• ESD >2000V per MIL-STD-883, Method 3015; >200V using  
machine model (C = 200pF, R = 0)  
RESETisanLVCMOSinputsinceitmustoperatepredictablyduringthe  
power-upphase.RESET,whichcanbeoperatedindependentofCLKand  
CLK, must be held in the low state during power-up in order to ensure  
predictable outputs (low state) before a stable clock has been applied.  
RESET, when in the low state, will disable all input receivers, reset all  
registers,andforcealloutputstoalowstate,beforeastableclockhasbeen  
applied. Withinputsheldlowandastableclockapplied,outputswillremain  
low during the Low-to-High transition of RESET.  
• Available in 56 pin VFQFPN and 64 pin TSSOP packages  
APPLICATIONS:  
• Ideally suited for stacked DIMM DDR registered applications  
• Along with CSPT857C/D, Zero Delay PLL Clock buffer, provides  
complete solution for DDR1 DIMMs  
FUNCTIONALBLOCKDIAGRAM  
51  
RESET  
48  
CLK  
49  
CLK  
45  
VREF  
35  
D1  
16  
Q1A  
1D  
C1  
32  
R
Q1B  
TO 12 OTHER CHANNELS  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
OCTOBER 2004  
1
c
2004 Integrated Device Technology, Inc.  
DSC 6517/1  

与IDT74SSTVN16859CNLG8相关器件

型号 品牌 获取价格 描述 数据表
IDT74SSTVN16859CPA IDT

获取价格

13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
IDT74SSTVN16859CPAG IDT

获取价格

13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
IDT74SSTVN16859CPAG8 IDT

获取价格

D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 13-Bit, True Output, PDSO64, GR
IDT74SSTVN16859NL IDT

获取价格

13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
IDT74SSTVN16859NL8 IDT

获取价格

D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 13-Bit, True Output, PQCC56, PL
IDT74SSTVN16859NLG IDT

获取价格

13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
IDT74SSTVN16859NLG8 IDT

获取价格

D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 13-Bit, True Output, PQCC56, GR
IDT74SSTVN16859PA IDT

获取价格

13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
IDT74SSTVN16859PA8 IDT

获取价格

D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 13-Bit, True Output, PDSO64, TS
IDT74SSTVN16859PAG IDT

获取价格

13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O