Datasheet > IDT75ALVCH16823PA

IDT75ALVCH16823PA

更新时间： 2024-11-11 04:44:31

品牌	Logo	应用领域
艾迪悌 - IDT		输出元件
页数	文件大小	规格书
7页	72K
描述
3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD

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IDT74ALVCH16823

3.3VCMOS18-BITBUS-INTERFACEFLIP-FLOPWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

IDT74ALVCH16823

3.3V CMOS 18-BIT

BUS-INTERFACE FLIP-

FLOP WITH 3-STATE OUT-

PUTS AND BUS-HOLD

DESCRIPTION:

FEATURES:

This18-bitbus-interfaceflip-flopisbuiltusingadvanceddualmetalCMOS

technology.TheALVCH16823features3-stateoutputsdesignedspecifically

fordrivinghighlycapacitiveorrelativelylow-impedanceloads.Thedeviceis

particularlysuitableforimplementingwiderbufferregisters,I/Oports,bidirec-

tional bus drivers with parity, and working registers.

• 0.5 MICRON CMOS Technology

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• VCC = 2.5V ± 0.2V

• CMOS power levels (0.4µ W typ. static)

• Rail-to-Rail output swing for increased noise margin

• Available in TSSOP package

TheALVCH16823canbeusedastwo9-bitflip-flopsorone18-bitflip-flop.

Withtheclock-enable(CLKEN)inputlow,theD-typeflip-flopsenterdataonthe

low-to-hightransitionsoftheclock.TakingCLKENhighdisablestheclockbuffer,

thuslatchingtheoutputs.Takingtheclear(CLR)inputlowcausestheQoutputs

togolowindependentlyoftheclock.

Abufferedoutput-enable(OE)inputcanbeusedtoplacethenineoutputs

ineitheranormallogicstate(highorlowlogiclevels)orahigh-impedancestate.

In the high-impedance state, the outputs neither load nor drive the bus lines

significantly. The high-impedance state and increased drive provide the

capabilitytodrivebuslineswithoutneedforinterfaceorpullupcomponents.The

OEinputdoesnotaffecttheinternaloperationoftheflip-flops.Olddatacanbe

retainedornewdatacanbeenteredwhiletheoutputsareinthehigh-impedance

state.

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Suitable for heavy loads

APPLICATIONS:

• 3.3V high speed systems

The ALVCH16823 has been designed with a ±24mA output driver. This

driveriscapableofdrivingamoderatetoheavyloadwhilemaintainingspeed

performance.

• 3.3V and lower voltage computing systems

The ALVCH16823 has “bus-hold” which retains the inputs’ last state

whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputsand

eliminatestheneedforpull-up/downresistor.

FUNCTIONALBLOCKDIAGRAM

1OE

2OE

1CLR

2CLR

1CLKEN

2CLKEN

1CLK

1D1

1Q1

2CLK

2D1

2Q1

TO 8 OTHER CHANNELS

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

JANUARY 2004

DSC-4237/2

12 3 4 5 6 7

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