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IDT74SSTVN16859PA PDF预览

IDT74SSTVN16859PA

更新时间: 2024-11-11 03:25:55
品牌 Logo 应用领域
艾迪悌 - IDT 触发器锁存器逻辑集成电路电视光电二极管PC
页数 文件大小 规格书
7页 65K
描述
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O

IDT74SSTVN16859PA 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP64,.32,20
针数:64Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.24
其他特性:220 MHZ FOR PC3200 OPERATION系列:SSTV
JESD-30 代码:R-PDSO-G64JESD-609代码:e0
长度:17 mm逻辑集成电路类型:D FLIP-FLOP
湿度敏感等级:1位数:13
功能数量:1端子数量:64
最高工作温度:70 °C最低工作温度:
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP64,.32,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):240电源:2.5 V
传播延迟(tpd):2.7 ns认证状态:Not Qualified
座面最大高度:1.1 mm子类别:Other Logic ICs
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:6.1 mm
最小 fmax:200 MHzBase Number Matches:1

IDT74SSTVN16859PA 数据手册

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13-BIT TO 26-BIT REGISTERED IDT74SSTVN16859  
BUFFER WITH SSTL I/O  
FEATURES:  
DESCRIPTION:  
• 1:2 registered output buffer  
The SSTVN16859 is a 13-bit to 26-bit registered buffer designed for  
• 2.3V to 2.7V operation for PC1600, PC2100, and PC2700  
• 2.5V to 2.7V operation for PC3200  
• Single bit propagation delay, TSSOP : 2.2ns, VFQFPN : 1.8ns  
• SSTL_2 Class I style data inputs/outputs  
• Differential CLK input  
RESET control compatible with LVCMOS levels  
• Latch-up performance exceeds 100mA  
• ESD >2000V per MIL-STD-883, Method 3015; >200V using  
machine model (C = 200pF, R = 0)  
2.3V-2.7VVDD forPC1600-PC2700and2.5V-2.7VVDD forPC3200, and  
supports low standby operation. All data inputs and outputs are SSTL_2  
level compatible with JEDEC standard for SSTL_2.  
RESETisanLVCMOSinputsinceitmustoperatepredictablyduringthe  
power-upphase.RESET,whichcanbeoperatedindependentofCLKand  
CLK, must be held in the low state during power-up in order to ensure  
predictable outputs (low state) before a stable clock has been applied.  
RESET, when in the low state, will disable all input receivers, reset all  
registers,andforcealloutputstoalowstate,beforeastableclockhasbeen  
applied. Withinputsheldlowandastableclockapplied,outputswillremain  
low during the Low-to-High transition of RESET.  
• Available in 56 pin VFQFPN and 64 pin TSSOP packages  
APPLICATIONS:  
• Ideally suited for stacked DIMM DDR registered applications  
• Along with CSPT857C/D, Zero Delay PLL Clock buffer, provides  
complete solution for DDR1 DIMMs  
FUNCTIONALBLOCKDIAGRAM  
51  
RESET  
48  
CLK  
49  
CLK  
45  
VREF  
35  
D1  
16  
Q1A  
1D  
C1  
32  
R
Q1B  
TO 12 OTHER CHANNELS  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
JANUARY 2004  
1
c
2004 Integrated Device Technology, Inc.  
DSC-6836/13  

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