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IDT72V3694L10PFG8 PDF预览

IDT72V3694L10PFG8

更新时间: 2024-10-31 15:44:23
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
36页 344K
描述
FIFO, 32KX36, 6.5ns, Synchronous, CMOS, PQFP128, TQFP-128

IDT72V3694L10PFG8 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFP包装说明:LFQFP,
针数:128Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.84最长访问时间:6.5 ns
其他特性:MAILBOX BYPASS REGISTER周期时间:10 ns
JESD-30 代码:R-PQFP-G128JESD-609代码:e3
长度:20 mm内存密度:1179648 bit
内存宽度:36湿度敏感等级:3
功能数量:1端子数量:128
字数:32768 words字数代码:32000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX36
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.45 V
最小供电电压 (Vsup):3.15 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:14 mmBase Number Matches:1

IDT72V3694L10PFG8 数据手册

 浏览型号IDT72V3694L10PFG8的Datasheet PDF文件第2页浏览型号IDT72V3694L10PFG8的Datasheet PDF文件第3页浏览型号IDT72V3694L10PFG8的Datasheet PDF文件第4页浏览型号IDT72V3694L10PFG8的Datasheet PDF文件第5页浏览型号IDT72V3694L10PFG8的Datasheet PDF文件第6页浏览型号IDT72V3694L10PFG8的Datasheet PDF文件第7页 
3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING  
16,384 x 36 x 2  
32,768 x 36 x 2  
65,536 x 36 x 2  
IDT72V3684  
IDT72V3694  
IDT72V36104  
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits  
(byte)  
Big- or Little-Endian format for word and byte bus sizes  
Master Reset clears data and configures FIFO, Partial Reset  
clears data but retains configuration settings  
FEATURES  
Memory storage capacity:  
IDT72V3684  
IDT72V3694  
IDT72V36104 – 65,536 x 36 x 2  
16,384 x 36 x 2  
32,768 x 36 x 2  
Mailbox bypass registers for each FIFO  
Clock frequencies up to 100 MHz (6.5ns access time)  
Two independent clocked FIFOs buffering data in opposite  
directions  
Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags  
functions) or First Word Fall Through Timing (using ORA, ORB,  
IRA, and IRB flag functions)  
Programmable Almost-Empty and Almost-Full flags; each has five  
default offsets (8, 16, 64, 256 and 1,024 )  
Serial or parallel programming of partial flags  
Retransmit Capability  
Free-running CLKA and CLKB may be asynchronous or coincident  
(simultaneous reading and writing of data on a single clock edge  
is permitted)  
Auto power down minimizes power dissipation  
Available in space saving 128-pin Thin Quad Flatpack (TQFP)  
Pin compatible to the lower density parts, IDT72V3624/72V3634/  
72V3644/72V3654/72V3664/72V3674  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
W/RA  
ENA  
Port-A  
Control  
Logic  
RAM ARRAY  
16,384 x 36  
32,768 x 36  
65,536 x 36  
36  
36  
MBA  
36  
FIFO1,  
Mail1  
Reset  
Logic  
MRS1  
PRS1  
Write  
Pointer  
Read  
Pointer  
36  
Status Flag  
Logic  
FFA/IRA  
EFB/ORB  
AEB  
AFA  
FIFO1  
FIFO2  
FS2  
FS0/SD  
FS1/SEN  
A0-A35  
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
B0-B35  
16  
Status Flag  
EFA/ORA  
FFB/IRB  
AFB  
Logic  
AEA  
36  
Read  
Pointer  
Write  
Pointer  
36  
FIFO2,  
Mail2  
Reset  
Logic  
MRS2  
PRS2  
RT1  
RTM  
RT2  
FIFO1 and  
FIFO2  
Retransmit  
Logic  
RAM ARRAY  
36  
36  
16,384 x 36  
32,768 x 36  
65,536 x 36  
CLKB  
CSB  
W/RB  
ENB  
MBB  
BE  
Port-B  
Control  
Logic  
Mail 2  
Register  
BM  
4677 drw01  
MBF2  
SIZE  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheSyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
FEBRUARY 2009  
1
©
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4677/8  

IDT72V3694L10PFG8 替代型号

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