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IDT72V51233L7.5BB PDF预览

IDT72V51233L7.5BB

更新时间: 2024-11-01 14:51:27
品牌 Logo 应用领域
艾迪悌 - IDT LTE先进先出芯片
页数 文件大小 规格书
50页 456K
描述
FIFO, 32KX18, 4ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256

IDT72V51233L7.5BB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:BGA,
针数:256Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.92最长访问时间:4 ns
其他特性:ALTERNATIVE MEMORY WIDTH:9-BIT周期时间:7.5 ns
JESD-30 代码:S-PBGA-B256JESD-609代码:e0
长度:17 mm内存密度:589824 bit
内存宽度:18湿度敏感等级:3
功能数量:1端子数量:256
字数:32768 words字数代码:32000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX18
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):225认证状态:Not Qualified
座面最大高度:3.5 mm最大供电电压 (Vsup):3.45 V
最小供电电压 (Vsup):3.15 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:20
宽度:17 mmBase Number Matches:1

IDT72V51233L7.5BB 数据手册

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3.3VMULTI-QUEUEFLOW-CONTROLDEVICES  
(4QUEUES)18BITWIDECONFIGURATION  
IDT72V51233  
IDT72V51243  
IDT72V51253  
589,824bits  
1,179,648bits  
2,359,296bits  
Individual, Active queue flags (OV, FF, PAE, PAF)  
4 bit parallel flag status on both read and write ports  
Provides continuous PAE and PAF status of up to 4 Queues  
Global Bus Matching - (All Queues have same Input Bus Width  
and Output Bus Width)  
User Selectable Bus Matching Options:  
- x18in to x18out  
- x9in to x18out  
FEATURES:  
Choose from among the following memory density options:  
IDT72V51233  
IDT72V51243  
IDT72V51253  
Total Available Memory = 589,824 bits  
Total Available Memory = 1,179,648 bits  
Total Available Memory = 2,359,296 bits  
Configurable from 1 to 4 Queues  
Queues may be configured at master reset from the pool of  
Total Available Memory in blocks of 512 x 18 or 1,024 x 9  
Independent Read and Write access per queue  
User programmable via serial port  
Default multi-queue device configurations  
-IDT72V51233: 8,192 x 18 x 4Q or 16,384 x 9 x 4Q  
-IDT72V51243: 16,384 x 18 x 4Q or 32,768 x 9 x 4Q  
-IDT72V51253: 32,768 x 18 x 4Q or 65,536 x 9 x 4Q  
100% Bus Utilization, Read and Write on every clock cycle  
166 MHz High speed operation (6ns cycle time)  
3.7ns access time  
- x18in to x9out  
- x9in to x9out  
FWFT mode of operation on read port  
Partial Reset, clears data in single Queue  
Expansion of up to 8 multi-queue devices in parallel is available  
JTAG Functionality (Boundary Scan)  
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm  
HIGH Performance submicron CMOS technology  
Industrial temperature range (-40°C to +85°C) is available  
FUNCTIONALBLOCKDIAGRAM  
MULTI-QUEUE FLOW-CONTROL DEVICE  
WADEN  
FSTR  
RADEN  
ESTR  
RDADD  
REN  
Q0  
WRADD  
WEN  
6
5
RCLK  
WCLK  
OE  
Q
out  
D
in  
x9, x18  
x9, x18  
DATA IN  
DATA OUT  
OV  
FF  
PAF  
Q3  
PAE  
PAFn  
4
PAEn  
4
5941 drw01  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.  
JUNE 2003  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-5941/9  

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