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IDT72V51236L6BBG PDF预览

IDT72V51236L6BBG

更新时间: 2024-10-31 14:51:27
品牌 Logo 应用领域
艾迪悌 - IDT LTE先进先出芯片
页数 文件大小 规格书
56页 536K
描述
FIFO, 16KX36, 3.7ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256

IDT72V51236L6BBG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:BGA
包装说明:17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256针数:256
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.84
Is Samacsys:N最长访问时间:3.7 ns
其他特性:ALTERNATIVE MEMORY WIDTH:9-BIT AND 18-BIT周期时间:6 ns
JESD-30 代码:S-PBGA-B256JESD-609代码:e1
长度:17 mm内存密度:589824 bit
内存宽度:36湿度敏感等级:3
功能数量:1端子数量:256
字数:16384 words字数代码:16000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:16KX36
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:3.5 mm最大供电电压 (Vsup):3.45 V
最小供电电压 (Vsup):3.15 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:17 mmBase Number Matches:1

IDT72V51236L6BBG 数据手册

 浏览型号IDT72V51236L6BBG的Datasheet PDF文件第2页浏览型号IDT72V51236L6BBG的Datasheet PDF文件第3页浏览型号IDT72V51236L6BBG的Datasheet PDF文件第4页浏览型号IDT72V51236L6BBG的Datasheet PDF文件第5页浏览型号IDT72V51236L6BBG的Datasheet PDF文件第6页浏览型号IDT72V51236L6BBG的Datasheet PDF文件第7页 
3.3VMULTI-QUEUEFLOW-CONTROLDEVICES  
(4QUEUES)36BITWIDECONFIGURATION  
589,824bits  
1,179,648bits  
2,359,296bits  
IDT72V51236  
IDT72V51246  
IDT72V51256  
4 bit parallel flag status on both read and write ports  
FEATURES:  
Provides continuous PAE and PAF status of up to 4 Queues  
Global Bus Matching - (All Queues have same Input Bus Width  
and Output Bus Width)  
User Selectable Bus Matching Options:  
- x36in to x36out  
- x18in to x36out  
- x9in to x36out  
- x36in to x18out  
- x36in to x9out  
Choose from among the following memory density options:  
IDT72V51236  
IDT72V51246  
IDT72V51256  
Total Available Memory = 589,824 bits  
Total Available Memory = 1,179,648 bits  
Total Available Memory = 2,359,296 bits  
Configurable from 1 to 4 Queues  
Queues may be configured at master reset from the pool of  
Total Available Memory in blocks of 256 x 36  
Independent Read and Write access per queue  
User programmable via serial port  
Default multi-queue device configurations  
-IDT72V51236: 4,096 x 36 x 4Q  
FWFT mode of operation on read port  
Packet mode operation  
Partial Reset, clears data in single Queue  
Expansion of up to 8 multi-queue devices in parallel is available  
JTAG Functionality (Boundary Scan)  
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm  
HIGH Performance submicron CMOS technology  
Industrial temperature range (-40°C to +85°C) is available  
-IDT72V51246: 8,192 x 36 x 4Q  
-IDT72V51256: 16,384 x 36 x 4Q  
100% Bus Utilization, Read and Write on every clock cycle  
166 MHz High speed operation (6ns cycle time)  
3.7ns access time  
Individual, Active queue flags (OV, FF, PAE, PAF, PR)  
FUNCTIONALBLOCKDIAGRAM  
MULTI-QUEUE FLOW-CONTROL DEVICE  
WADEN  
FSTR  
RADEN  
ESTR  
RDADD  
REN  
Q0  
WRADD  
WEN  
6
5
RCLK  
WCLK  
OE  
Q
out  
D
in  
x9, x18, x36  
DATA OUT  
x9, x18, x36  
DATA IN  
OV  
FF  
PAF  
Q3  
PR  
PAE  
PAFn  
4
PAEn/PRn  
4
5937 drw01  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc  
JUNE 2003  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-5937/9  

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