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IDT72V275L15PFI PDF预览

IDT72V275L15PFI

更新时间: 2024-11-13 23:05:11
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
25页 206K
描述
3.3 VOLT CMOS SuperSync FIFO

IDT72V275L15PFI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:PLASTIC, TQFP-64针数:64
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.26
最长访问时间:10 ns最大时钟频率 (fCLK):66.7 MHz
周期时间:15 nsJESD-30 代码:S-PQFP-G64
JESD-609代码:e0长度:14 mm
内存密度:589824 bit内存集成电路类型:OTHER FIFO
内存宽度:18湿度敏感等级:3
功能数量:1端子数量:64
字数:32768 words字数代码:32000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:32KX18
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP64,.66SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.02 A
子类别:FIFOs最大压摆率:0.06 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

IDT72V275L15PFI 数据手册

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3.3 VOLT CMOS SuperSync FIFO™  
32,768 X 18  
65,536 X 18  
IDT72V275  
IDT72V285  
Slim Thin Quad Flat Pack (STQFP)  
High-performance submicron CMOS technology  
Industrial temperature range (-40°C to +85°C) is available  
ꢀEATURES:  
Choose among the following memory organizations:  
IDT72V275  
IDT72V285  
32,768 x 18  
65,536 x 18  
DESCRIPTION:  
Pin-compatible with the IDT72V255/72V265 SuperSync FIFOs  
10ns read/write cycle time (6.5ns access time)  
Fixed, low first word data latency time  
Auto power down minimizes standby power consumption  
Master Reset clears entire FIFO  
Partial Reset clears data, but retains programmable  
settings  
Retransmit operation with fixed, low first word data  
latency time  
Empty, Full and Half-Full flags signal FIFO status  
Programmable Almost-Empty and Almost-Full flags, each flag can  
default to one of two preselected offsets  
Program partial flags by either serial or parallel means  
Select IDT Standard timing (using EF and FF flags) or First Word  
Fall Through timing (using OR and IR flags)  
The IDT72V275/72V285 are exceptionally deep, high speed, CMOS  
First-In-First-Out (FIFO) memories with clocked read and write controls.  
These FIFOs offer numerous improvements over previous SuperSync  
FIFOs, includingthe following:  
Thelimitationofthefrequencyofoneclockinputwithrespecttotheother  
has beenremoved. TheFrequencySelectpin(FS)has beenremoved,  
thusitisnolongernecessarytoselectwhichofthetwoclockinputs,RCLK  
or WCLK, is running at the higher frequency.  
The period required by the retransmit operation is now fixed and short.  
Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittento  
an empty FIFO to the time it can be read, is now fixed and short. (The  
variable clock cycle counting delay associated with the latency period  
found on previous SuperSync devices has been eliminated on this  
SuperSyncfamily.)  
Output enable puts data outputs into high impedance state  
Easily expandable in depth and width  
Independent Read and Write clocks (permit reading and writing  
simultaneously)  
SuperSyncFIFOsareparticularlyappropriatefornetwork,video,telecom-  
munications,datacommunicationsandotherapplicationsthatneedtobuffer  
largeamountsofdata.  
Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin  
ꢀUNCTIONAL BLOCK DIAGRAM  
D0 -D17  
WEN  
WCLK  
LD  
SEN  
OFFSET REGISTER  
INPUT REGISTER  
FF/IR  
PAF  
EF/OR  
PAE  
HF  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
FWFT/SI  
RAM ARRAY  
32,768 x 18  
65,536 x 18  
WRITE POINTER  
READ POINTER  
READ  
CONTROL  
LOGIC  
RT  
OUTPUT REGISTER  
MRS  
PRS  
RESET  
LOGIC  
RCLK  
REN  
4512 drw 01  
Q0 -Q17  
OE  
SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
APRIL 2001  
2001 Integrated Device Technology, Inc.  
DSC-4512/1  

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