2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 72-BIT CONFIGURATIONS
16,384 x 72, 32,768 x 72,
65,536 x 72, 131,072 x 72
IDT72T7285, IDT72T7295,
IDT72T72105, IDT72T72115
• User selectable input and output port bus-sizing
FEATURES:
- x72 in to x72 out
- x72 in to x36 out
- x72 in to x18 out
- x36 in to x72 out
• Choose among the following memory organizations:
IDT72T7285
IDT72T7295
IDT72T72105
IDT72T72115
16,384 x 72
32,768 x 72
65,536 x 72
131,072 x 72
- x18 in to x72 out
• Big-Endian/Little-Endian user selectable byte representation
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Up to 225 MHz Operation of Clocks
• User selectable HSTL/LVTTL Input and/or Output
• Read Enable & Read Clock Echo outputs aid high speed operation
• User selectable Asynchronous read and/or write port timing
• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
• 3.3V Input tolerant
• Mark & Retransmit, resets read pointer to user marked position
• Write Chip Select (WCS) input disables Write Port HSTL inputs
• Read Chip Select (RCS) synchronous to RCLK
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Program programmable flags by either serial or parallel means
• Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• JTAG port, provided for Boundary Scan function
• Available in 324-pin (19mm x 19mm)Plastic Ball Grid Array (PBGA)
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
• Separate SCLK input for Serial programming of flag offsets
FUNCTIONALBLOCKDIAGRAM
D0 -Dn (x72, x36 or x18)
LD SEN
SCLK
WEN
WCLK/WR
WCS
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
WRITE CONTROL
LOGIC
ASYW
FLAG
LOGIC
RAM ARRAY
16,384 x 72
32,768 x 72
65,536 x 72
131,072 x 72
WRITE POINTER
BE
CONTROL
LOGIC
READ POINTER
IP
BM
IW
OW
BUS
CONFIGURATION
RT
READ
CONTROL
LOGIC
MARK
ASYR
MRS
PRS
OUTPUT REGISTER
RESET
LOGIC
TCK
TRST
TMS
TDO
JTAG CONTROL
(BOUNDARY SCAN)
RCLK/RD
REN
RCS
TDI
Vref
WHSTL
RHSTL
SHSTL
HSTL I/0
CONTROL
EREN
OE
5994 drw01
Q0 -Qn (x72, x36 or x18)
ERCLK
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SEPTEMBER 2003
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5994/12