Datasheet > 存储 > FIFO> IDT72T51246L5BBI

IDT72T51246L5BBI

更新时间： 2024-11-12 05:11:59

品牌	Logo	应用领域
艾迪悌 - IDT		控制器
页数	文件大小	规格书
62页	595K
描述
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits

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IDT72T51246L5BBI 数据手册

ADVANCE INFORMATION

2.5V MULTI-QUEUE FLOW-CONTROL DEVICES

(4 QUEUES) 36 BIT WIDE CONFIGURATION

589,824 bits, 1,179,648 bits and 2,359,296 bits

IDT72T51236

IDT72T51246

IDT72T51256

•

4 bit parallel flag status on both read and write ports

FEATURES:

Provides continuous PAE and PAF status of up to 4 Queues

Global Bus Matching - (All Queues have same Input Bus Width

and Output Bus Width)

User Selectable Bus Matching Options:

- x36in to x36out

- x18in to x36out

- x9in to x36out

- x36in to x18out

- x36in to x9out

FWFT mode of operation on read port

Packet mode operation

Partial Reset, clears data in single Queue

Expansion of up to 8 multi-queue devices in parallel is available

Power Down Input provides additional power savings in HSTL

and eHSTL modes.

JTAG Functionality (Boundary Scan)

Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm

HIGH Performance submicron CMOS technology

Industrial temperature range (-40°C to +85°C) is available

•

Choose from among the following memory density options:

IDT72T51236

IDT72T51246

IDT72T51256



Total Available Memory = 589,824 bits

Total Available Memory = 1,179,648 bits

Total Available Memory = 2,359,296 bits

•

Configurable from 1 to 4 Queues

Queues may be configured at master reset from the pool of

Total Available Memory in blocks of 256 x 36

Independent Read and Write access per queue

User programmable via serial port

User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL

Default multi-queue device configurations

-IDT72T51236: 4,096 x 36 x 4Q

•

-IDT72T51246: 8,192 x 36 x 4Q

-IDT72T51256: 16,384 x 36 x 4Q

•

100% Bus Utilization, Read and Write on every clock cycle

200 MHz High speed operation (5ns cycle time)

3.6ns access time

Echo Read Enable & Echo Read Clock Outputs

Individual, Active queue flags (OV, FF, PAE, PAF, PR)

•

FUNCTIONALBLOCKDIAGRAM

MULTI-QUEUE FLOW-CONTROL DEVICE

RADEN

ESTR

WADEN

FSTR

RDADD

WRADD

WEN

REN

RCLK

EREN

WCLK

ERCLK

out

x9, x18, x36

DATA IN

DATA OUT

PAF

PAFn

PAE

PAEn

PRn

6116 drw01

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc

NOVEMBER 2003

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

DSC-6116/2

12 3 4 5 6 7...62

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与IDT72T51246L5BBI相关器件

型号	品牌	获取价格	描述	数据表
IDT72T51246L6BB	IDT	获取价格	2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1
IDT72T51246L6BB8	IDT	获取价格	FIFO, 32KX36, 3.7ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
IDT72T51246L6BBI	IDT	获取价格	2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1
IDT72T51246L7-5BBI	IDT	获取价格	FIFO, 32KX36, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
IDT72T51248L6-7BB	IDT	获取价格	FIFO, 32KX40, 3.8ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
IDT72T51248L6-7BBGI	IDT	获取价格	FIFO, 32KX40, 3.8ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
IDT72T51248L6-7BBI	IDT	获取价格	FIFO, 32KX40, 3.8ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
IDT72T51253	IDT	获取价格	2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits
IDT72T51253L5BB	IDT	获取价格	2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits
IDT72T51253L5BB8	IDT	获取价格	FIFO, 128KX18, 3.6ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256

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