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IDT72T51248L6-7BBI PDF预览

IDT72T51248L6-7BBI

更新时间: 2024-11-13 08:35:51
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
56页 538K
描述
FIFO, 32KX40, 3.8ns, Synchronous, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324

IDT72T51248L6-7BBI 数据手册

 浏览型号IDT72T51248L6-7BBI的Datasheet PDF文件第2页浏览型号IDT72T51248L6-7BBI的Datasheet PDF文件第3页浏览型号IDT72T51248L6-7BBI的Datasheet PDF文件第4页浏览型号IDT72T51248L6-7BBI的Datasheet PDF文件第5页浏览型号IDT72T51248L6-7BBI的Datasheet PDF文件第6页浏览型号IDT72T51248L6-7BBI的Datasheet PDF文件第7页 
2.5VMULTI-QUEUEDDRFLOW-CONTROLDEVICES  
40 BITS WIDE WITH FIXED 4 QUEUES  
8,192 x 40 x 4, 16,384 x 40 x 4  
IDT72T51248  
IDT72T51258  
IDT72T51268  
and 32,768 x 40 x 4  
Write Chip Select WCS input for write port  
Read Chip Select RCS input for read port  
User Selectable IDT Standard mode (using EF and FF) or FWFT  
mode (using IR and OR)  
All 4 Queues have dedicated flag outputs FF/IR, EF/OR, PAF  
and PAE  
A Composite Full/ Input Ready Flag gives status of the queue  
selected on the write port  
A Composite Empty/ Output Ready flag gives status of the  
queue selected on the read port  
Programmable Almost Empty and Almost Full flags per Queue  
Dedicated Serial Port for flag programming  
A Partial Reset is provided for each queue  
Power Down pin minimizes power consumption  
2.5V Supply Voltage  
Available in a 324-pin Plastic Ball Grid Array (PBGA)  
19mmx19mm,1mmPitch  
JTAG port provides boundary scan function and optional  
programming mode  
Low Power, High Performance CMOS technology  
Industrial temperature range (-40°C to +85°C)  
FEATURES  
The multi-queue DDR flow-control device contains 4 Queues  
each queue has a fixed size of:  
IDT72T51248 — 8,192 x 40 or 16,384 x 20 or 32,768 x 10  
IDT72T51258 — 16,384 x 40 or 32,768 x 20 or 65,536 x 10  
IDT72T51268 — 32,768 x 40 or 65,536 x 20 or 131,072 x 10  
Write to and Read from the same queue or different queues  
simultaneously via totally independent ports  
Up to 200MHz operating frequency or 8Gbps throughput in SDR mode  
Up to 100MHz operating frequency or 8Gbps throughput in DDR mode  
User selectable Single Data Rate (SDR) or Double Data Rate  
(DDR) modes on both the write port and read port  
100% Bus Utilization, Read and Write on every clock cycle  
Global Bus Matching - All Queues have same Input bus width  
and same Output bus width  
User Selectable Bus Matching options:  
- x40in to x40out  
- x20in to x40out  
- x10in to x40out  
- x40in to x20out  
- x20in to x20out  
- x10in to x20out  
- x40in to x10out  
- x20in to x10out  
- x10in to x10out  
All I/O is LVTTL/ HSTL/ eHSTL user selectable  
3.3V tolerant inputs in LVTTL mode  
ERCLK & EREN Echo outputs on read port  
FUNCTIONALBLOCKDIAGRAM  
MULTI-QUEUE DDR FLOW-CONTROL DEVICE  
WCLK  
WEN  
WCS  
RCLK  
REN  
RCS  
OE  
8,192 x 40  
16,384 x40  
32,768 x 40  
IS[1:0]  
OS[1:0]  
2
2
Queue 0  
8,192 x 40  
16,384 x40  
32,768 x 40  
D[39:0]  
Q[39:0]  
Queue 1  
Data In  
Data Out  
x10,x20,x40  
x10,x20,x40  
8,192 x 40  
16,384 x40  
32,768 x 40  
Queue 2  
8,192 x 40  
16,384 x40  
32,768 x 40  
EF0/OR0  
PAE0  
EF1/OR1  
PAE1  
EF2/OR2  
PAE2  
FF0/IR0  
PAF0  
FF1/IR1  
PAF1  
FF2/IR2  
PAF2  
Queue 3  
EF3/OR3  
PAE3  
FF3/IR3  
PAF3  
CEF/COR  
CFF/CIR  
6159 drw01  
MARCH 2005  
IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology,Inc  
1
2005 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-6159/4  

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