Datasheet > 存储 > FIFO> IDT72401L45D

IDT72401L45D

更新时间： 2024-11-10 22:57:23

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
9页	99K
描述
CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT

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IDT72401L45D 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	DIP	包装说明：	0.300 INCH, CERDIP-16
针数：	16	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	5.88	最长访问时间：	19 ns
其他特性：	FALL THRU 30NS	最大时钟频率 (fCLK)：	45 MHz
周期时间：	22.22 ns	JESD-30 代码：	R-GDIP-T16
JESD-609代码：	e0	长度：	20.066 mm
内存密度：	256 bit	内存集成电路类型：	OTHER FIFO
内存宽度：	4	功能数量：	1
端子数量：	16	字数：	64 words
字数代码：	64	工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	64X4	输出特性：	TOTEM POLE
可输出：	NO	封装主体材料：	CERAMIC, GLASS-SEALED
封装代码：	DIP	封装等效代码：	DIP16,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
并行/串行：	PARALLEL	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	5.08 mm
子类别：	FIFOs	最大压摆率：	0.0875 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
宽度：	7.62 mm	Base Number Matches：	1

IDT72401L45D 数据手册

IDT72401

IDT72402

IDT72403

IDT72404

CMOS PARALLEL FIFO

64 x 4-BIT AND 64 x 5-BIT

Integrated Device Technology, Inc.

Output Enable (OE) pin. The FlFOs accept 4-bit or 5-bit data

at the data input (D0-D3, 4). The stored data stack up on a first-

in/first-out basis.

FEATURES:

• First-ln/First-Out Dual-Port memory

• 64 x 4 organization (IDT72401/03)

• 64 x 5 organization (IDT72402/04)

• IDT72401/02 pin and functionally compatible with

MMI67401/02

• RAM-based FIFO with low falI-through time

• Low-power consumption

— Active: 175mW (typ.)

A Shift Out (SO) signal causes the data at the next to last

word to be shifted to the output while all other data shifts down

one location in the stack. The Input Ready (IR) signal acts like

a flag to indicate when the input is ready for new data

(IR = HIGH) or to signal when the FIFO is full (IR = LOW). The

Input Ready signal can also be used to cascade multiple

devices together. The Output Ready (OR) signal is a flag to

indicate that the output remains valid data (OR = HIGH) or to

indicate that the FIFO is empty (OR = LOW). The Output

Readycanalsobeusedtocascademultipledevicestogether.

Width expansion is accomplished by logically ANDing the

Input Ready (IR) and Output Ready (OR) signals to form

composite signals.

• Maximum shift rate — 45MHz

• High data output drive capability

• Asynchronous and simultaneous read and write

• Fully expandable by bit width

• Fully expandable by word depth

• IDT72403/04 have Output Enable pin to enable output

data

Depth expansion is accomplished by tying the data inputs

of one device to the data outputs of the previous device. The

Input Ready pin of the receiving device is connected to the

Shift Out pin of the sending device and the Output Ready pin

of the sending device is connected to the Shift In pin of the

receiving device.

Reading and writing operations are completely asynchro-

nous allowing the FIFO to be used as a buffer between two

digital machines of widely varying operating frequencies. The

45MHz speed makes these FlFOs ideal for high-speed

communication and controller applications.

• High-speed data communications applications

• High-performance CMOS technology

• Available in CERDIP, plastic DIP and SOIC

• Military product compliant to MlL-STD-883, Class B

• Standard Military Drawing #5962-86846 and

5962-89523 is listed on this function.

• Industrial temperature range (–40°C to +85°C) is avail-

able, tested to military electrical specifications

DESCRIPTION:

The IDT72401 and IDT72403 are asynchronous high-

performance First-ln/First-Out memories organized 64 words

by 4 bits. The IDT72402 and IDT72404 are asynchronous

high-performance First-ln/First-Out memories organized as

64 words by 5 bits. The IDT72403 and IDT72404 also have an

Military grade product is manufactured in compliance with

the latest revision of MIL-STD-883, Class B.

FUNCTIONAL BLOCK DIAGRAM

OUTPUT

ENABLE

INPUT

CONTROL

LOGIC

OE (IDT72403 and

IDT72404)

WRITE POINTER

WRITE MULTIPLEXER

D_0-3

D₄

(IDT72402

and IDT72404)

Q_0-3

MEMORY

ARRAY

DATA_IN

DATA_OUT

(IDT72402 and

IDT72404)

READ MULTIPLEXER

READ POINTER

MASTER

RESET

OUTPUT

CONTROL

LOGIC

2747 drw 01

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FAST is a trademark of National Semiconductor, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SEPTEMBER 1996

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

1996 Integrated Device Technology, Inc.

DSC-2747/7

5.01

12 3 4 5 6 7...9

中文翻译

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与IDT72401L45D相关器件

型号	品牌	获取价格	描述	数据表
IDT72401L45DB	IDT	获取价格	CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
IDT72401L45DG	IDT	获取价格	FIFO, 64X4, Asynchronous, CMOS, CDIP16
IDT72401L45L	ETC	获取价格	x4 Asynchronous FIFO
IDT72401L45P	IDT	获取价格	CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
IDT72401L45PB	IDT	获取价格	CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
IDT72401L45PDG	IDT	获取价格	FIFO, 64X4, Asynchronous, CMOS, PDIP16
IDT72401L45PG	IDT	获取价格	FIFO, 64X4, 19ns, Asynchronous, CMOS, PDIP16, 0.300 INCH, PLASTIC, DIP-16
IDT72401L45SO	IDT	获取价格	CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT
IDT72401L45SO8	IDT	获取价格	FIFO, 64X4, 19ns, Asynchronous, CMOS, PDSO16, SOIC-16
IDT72401L45SOB	IDT	获取价格	CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT

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