IDT723623/723633/723643BUS-MATCHINGSyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
COMMERCIALTEMPERATURERANGE
CommunicationbetweeneachportmaybypasstheFIFOviatwomailbox
registers.Themailboxregisters'widthmatchestheselectedPortBbuswidth.
Eachmailboxregisterhas aflag(MBF1andMBF2)tosignalwhennewmail
has beenstored.
TwokindsofresetareavailableontheseFIFOs: ResetandPartialReset.
Resetinitializesthereadandwritepointerstothefirstlocationofthememory
arrayandselectsserialflagprogramming,parallelflagprogramming,orone
ofthreepossibledefaultflagoffsetsettings,8,16or64.
DESCRIPTION(CONTINUED)
The256/512/1,024x36dual-portSRAMFIFObuffersdatafromportAtoport
B.FIFOdataonPortBcanoutputin36-bit,18-bit,or9-bitformatswithachoice
ofBig-orLittle-Endianconfigurations.
These devices are synchronous (clocked) FIFOs, meaning each port
employsasynchronousinterface.Alldatatransfersthroughaportaregated
totheLOW-to-HIGHtransitionofaportclockbyenablesignals.Theclocksfor
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectionalinterfacebetweenmicroprocessorsand/orbuseswithsynchro-
nouscontrol.
PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe
memory. Unlike Reset, any settings existing prior to Partial Reset (i.e.,
programmingmethodandpartialflagdefaultoffsets)areretained. PartialReset
PIN CONꢀIGURATION
INDEX
1
CLKB
102
W/RA
2
Vcc
101
ENA
3
Vcc
100
CLKA
4
B35
99
GND
5
B34
98
A35
6
B33
97
A34
7
B32
96
A33
8
9
GND
GND
B31
B30
B29
B28
B27
B26
Vcc
A32
Vcc
A31
A30
GND
A29
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
A28
A27
A26
A25
A24
A23
B25
B24
BM
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
SIZE
Vcc
BE/FWFT
GND
A22
Vcc
A21
A20
A19
A18
GND
A17
A16
A15
B15
B14
B13
B12
GND
B11
B10
A14
A13
Vcc
A12
GND
A11
A10
3269 drw02
TQFP (PK128-1, order code: PF)
TOP VIEW
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