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IDT723624L12PF9 PDF预览

IDT723624L12PF9

更新时间: 2024-02-01 16:46:13
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
35页 406K
描述
FIFO, 256X36, 8ns, Synchronous, CMOS, PQFP128, TQFP-128

IDT723624L12PF9 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP,针数:128
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.5
最长访问时间:8 ns其他特性:MAIL BOX
周期时间:12 nsJESD-30 代码:R-PQFP-G128
JESD-609代码:e0长度:20 mm
内存密度:9216 bit内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:128字数:256 words
字数代码:256工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256X36可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):240
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

IDT723624L12PF9 数据手册

 浏览型号IDT723624L12PF9的Datasheet PDF文件第2页浏览型号IDT723624L12PF9的Datasheet PDF文件第3页浏览型号IDT723624L12PF9的Datasheet PDF文件第4页浏览型号IDT723624L12PF9的Datasheet PDF文件第5页浏览型号IDT723624L12PF9的Datasheet PDF文件第6页浏览型号IDT723624L12PF9的Datasheet PDF文件第7页 
CMOS SyncBiFIFOTM WITH BUS-MATCHING  
256 x 36 x 2,  
512 x 36 x 2,  
1,024 x 36 x 2  
IDT723624  
IDT723634  
IDT723644  
Serial or parallel programming of partial flags  
FEATURES:  
Port B bus sizing of 36-bits (long word), 18-bits (word) and  
9-bits (byte)  
Big- or Little-Endian format for word and byte bus sizes  
Master Reset clears data and configures FIFO, Partial Reset  
clears data but retains configuration settings  
Mailbox bypass registers for each FIFO  
Free-running CLKA and CLKB may be asynchronous or coinci-  
dent (simultaneous reading and writing of data on a single clock  
edge is permitted)  
Auto power down minimizes power dissipation  
Available in space saving 128-pin Thin Quad Flatpack (TQFP)  
Memory storage capacity:  
IDT723624  
IDT723634  
IDT723644  
256 x 36 x 2  
512 x 36 x 2  
1,024 x 36 x 2  
Clock frequencies up to 83 MHz (8 ns access time)  
Two independent clocked FIFOs buffering data in opposite  
directions  
Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags  
functions) or First Word Fall Through Timing (using ORA, ORB,  
IRA, and IRB flag functions)  
Programmable Almost-Empty and Almost-Full flags; each has  
three default offsets (8, 16 and 64)  
Industrial temperature range (–40°C to +85°C) is available  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
Port-A  
Control  
Logic  
CSA  
W/RA  
ENA  
RAM ARRAY  
256 x 36  
36  
36  
MBA  
512 x 36  
1,024 x 36  
36  
FIFO1,  
Mail1  
Reset  
Logic  
MRS1  
PRS1  
Write  
Pointer  
Read  
Pointer  
36  
Status Flag  
Logic  
EFB/ORB  
AEB  
FFA/IRA  
AFA  
FIFO1  
FIFO2  
SPM  
FS0/SD  
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
FS1/SEN  
A
0-A35  
B0-B35  
10  
EFA/ORA  
Status Flag  
Logic  
FFB/IRB  
AFB  
AEA  
36  
Read  
Pointer  
Write  
Pointer  
36  
FIFO2,  
Mail2  
Reset  
Logic  
MRS2  
PRS2  
RAM ARRAY  
256 x 36  
36  
36  
512 x 36  
CLKB  
CSB  
W/RB  
ENB  
MBB  
BE  
1,024 x 36  
Port-B  
Control  
Logic  
Mail 2  
Register  
BM  
SIZE  
MBF2  
3270 drw01  
IDTandtheIDTlogoaretrademarkofIntegratedDeviceTechnology,Inc.SyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIALTEMPERATURERANGE  
AUGUST 2001  
1
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-3270/3  

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