Datasheet > 存储 > FIFO> IDT72201L35J

IDT72201L35J

更新时间： 2024-09-15 05:12:03

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
19页	200K
描述
CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9

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IDT72201L35J 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFJ	包装说明：	0.050 INCH PITCH, PLASTIC, LCC-32
针数：	32	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.71
风险等级：	5.71	最长访问时间：	20 ns
最大时钟频率 (fCLK)：	28.5 MHz	周期时间：	35 ns
JESD-30 代码：	R-PQCC-J32	JESD-609代码：	e0
长度：	13.97 mm	内存密度：	2304 bit
内存集成电路类型：	OTHER FIFO	内存宽度：	9
湿度敏感等级：	1	功能数量：	1
端子数量：	32	字数：	256 words
字数代码：	256	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256X9	输出特性：	3-STATE
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC32,.5X.6
封装形状：	RECTANGULAR	封装形式：	CHIP CARRIER
并行/串行：	PARALLEL	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	3.55 mm
最大待机电流：	0.08 A	子类别：	FIFOs
最大压摆率：	0.08 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	宽度：	11.43 mm
Base Number Matches：	1

IDT72201L35J 数据手册

IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO

MILITARY AND COMMERCIAL TEMPERATURE RANGES

^{64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9}CMOS SyncFIFO

IDT72421

IDT72201

IDT72211

IDT72221

IDT72231

IDT72241

64 X 9, 256 x 9, 512 x 9,

1024 X 9, 2048 X 9 and 4096 x 9

Integrated Device Technology, Inc.

FEATURES:

• 64 x 9-bit organization (IDT72421)

• 256 x 9-bit organization (IDT72201)

• 512 x 9-bit organization (IDT72211)

• 1024 x 9-bit organization (IDT72221)

• 2048 x 9-bit organization (IDT72231)

• 4096 x 9-bit organization (IDT72241)

Out (FIFO) memories with clocked read and write controls.

The IDT72421/72201/72211/72221/72231/72241 have a 64,

256, 512, 1024, 2048, and 4096 x 9-bit memory array,

respectively. These FIFOs are applicable for a wide variety of

data buffering needs such as graphics, local area networks

and interprocessor communication.

These FIFOs have 9-bit input and output ports. The input

port is controlled by a free-running clock (WCLK), and two

write enable pins (WEN1, WEN2). Data is written into the

Synchronous FIFO on every rising clock edge when the write

enable pins are asserted. The output port is controlled by

another clock pin (RCLK) and two read enable pins (REN1,

REN2). The read clock can be tied to the write clock for single

clockoperationorthetwoclockscanrunasynchronousofone

another for dual-clock operation. An output enable pin (OE) is

provided on the read port for three-state control of the output.

The Synchronous FIFOs have two fixed flags, Empty (EF)

and Full (FF). Two programmable flags, Almost-Empty (PAE)

and Almost-Full (PAF), are provided for improved system

control. TheprogrammableflagsdefaulttoEmpty+7andFull-

7 for PAE and PAF, respectively. The programmable flag

offset loading is controlled by a simple state machine and is

initiated by asserting the load pin (LD).

• 12 ns read/write cycle time (IDT72421/72201/72211)

• 15 ns read/write cycle time (IDT72221/72231/72241)

• Read and write clocks can be independent

• Dual-Ported zero fall-through time architecture

• Empty and Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags can

be set to any depth

• Programmable Almost-Empty and Almost-Full flags

default to Empty+7, and Full-7, respectively

• Output enable puts output data bus in high-impedance

state

• Advanced submicron CMOS technology

• Available in 32-pin plastic leaded chip carrier (PLCC),

ceramic leadless chip carrier (LCC), and 32-pin Thin

Quad Flat Pack (TQFP)

• For Through-Hole product please see the IDT72420/

72200/72210/72220/72230/72240 data sheet

• Military product compliant to MIL-STD-883, Class B

The IDT72421/72201/72211/72221/72231/72241 are

fabricated using IDT’s high-speed submicron CMOS

technology. Military grade product is manufactured in

compliance with the latest revision of MIL-STD-883, Class B.

DESCRIPTION:

The IDT72421/72201/72211/72221/72231/72241

SyncFIFO are very high-speed, low-power First-In, First-

FUNCTIONAL BLOCK DIAGRAM

D0 - D8

WCLK

WEN1

WEN2

INPUT REGISTER

OFFSET REGISTER

FLAG

LOGIC

PAE

PAF

WRITE CONTROL

LOGIC

RAM ARRAY

64 x 9, 256 x 9,

512 x 9, 1024 x 9,

2048 x 9, 4096 x 9

WRITE POINTER

READ POINTER

READ CONTROL

LOGIC

OUTPUT REGISTER

RESET LOGIC

RCLK

REN1

REN2

2655 drw 01

Q0 - Q8

SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DECEMBER 1995

1996 Integrated Device Technology, Inc

DSC-2655/6

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. 5.07

12 3 4 5 6 7...19

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与IDT72201L35J相关器件

型号	品牌	获取价格	描述	数据表
IDT72201L35J8	IDT	获取价格	FIFO, 256X9, Synchronous, CMOS, PQCC32, 0.050 INCH PITCH, PLASTIC, LCC-32
IDT72201L35JB	IDT	获取价格	CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
IDT72201L35JSCDS-W	ETC	获取价格	x9 Synchronous FIFO
IDT72201L35L	IDT	获取价格	CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
IDT72201L35L8	IDT	获取价格	FIFO, 256X9, Synchronous, CMOS, CQCC32, LCC-32
IDT72201L35LB	IDT	获取价格	CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
IDT72201L35LB8	IDT	获取价格	FIFO, 256X9, Synchronous, CMOS, CQCC32, LCC-32
IDT72201L35PF	IDT	获取价格	CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
IDT72201L35PFB	IDT	获取价格	CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
IDT72201L50J	IDT	获取价格	CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9

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