IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 36, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
V
A
A
A
A
A
A
A
A
B
C
D
E
F
ADSP
ADSC
CS (4)
0
NC
NC
3
2
9
A17
NC
NC
7
A
DD
V
12
A
15
A
16
I/O
P3
I/O
SS
SS
SS
SS
SS
SS
P2
I/O
15
I/O
V
V
V
NC
CE
V
V
V
17
I/O
18
I/O
13
I/O
14
I/O
DDQ
V
19
I/O
12
I/O
DDQ
V
OE
20
21
11
10
I/O
I/O
I/O
I/O
G
H
J
2
3
BW
ADV
GW
BW
22
I/O
23
I/O
SS
V
SS
V
9
I/O
8
I/O
DDQ
DD
DD
V
DD
DDQ
V
V
V
NC
NC
V
24
26
SS
4
SS
6
7
I/O
I/O
V
CLK
NC
V
I/O
I/O
K
L
25
I/O
27
I/O
4
I/O
5
I/O
1
BW
BW
DDQ
28
SS
SS
SS
SS
SS
SS
3
I/O
DDQ
V
I/O
V
V
V
V
V
V
V
M
N
P
R
T
BWE
29
I/O
30
I/O
1
0
2
I/O
1
I/O
A
31
P4
0
I/O
P1
I/O
I/O
NC
NC
I/O
A
(1)
NC
5
DD
11
13
A
A
V
VDD / NC
LBO
(2)
10
A
14
A
NC
A
NC
DNU
ZZ
,
(3)
(3)
(3)
(3)
(3)
DDQ
V
DDQ
V
DNU
DNU
U
DNU
DNU
5311 drw 04
Top View
Pin Configuration 512K x 18, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
A
A
ADSP
ADSC
(4)
3
2
9
NC
NC
CS
A
18
NC
NC
NC
0
7
A
DD
V
13
A
17
A
8
SS
SS
SS
SS
SS
SS
SS
7
I/O
NC
NC
V
V
V
NC
V
V
V
V
I/O
NC
9
I/O
6
I/O
CE
OE
DDQ
V
5
DDQ
V
NC
I/O
NC
10
I/O
4
I/O
G
H
J
NC
I/O
BW
2
ADV
GW
11
SS
SS
3
I/O
NC
V
V
NC
DDQ
V
DD
DD
V
DD
DDQ
V
V
NC
V
NC
12
SS
SS
2
I/O
K
L
NC
I/O
I/O
NC
V
CLK
NC
V
NC
13
SS
1
I/O
V
NC
1
BW
DDQ
14
SS
SS
V
DDQ
V
M
N
P
R
T
V
I/O
NC
I/O
V
V
V
NC
BWE
15
SS
SS
1
SS
0
I/O
I/O
NC
A
A
V
V
NC
I/O
P2
0
SS
P1
NC
(1)
5
DD
V
12
11
NC
NC
DDQ
A
V
DD / NC
A
NC
LBO
(2)
,
10
15
14
A
A
A
NC
A
ZZ
(3)
(3)
(3)
(3)
(3)
DDQ
V
5311 drw 05
DNU
DNU
U
V
DNU
DNU
DNU
Top View
NOTES:
1. R5 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. T7 can be left unconnected and the device will always remain in active mode.
3. Pin U6 will be internally pulled to VDD if not actively driven. To disable the TAP controller without interfering with normal operation, TRST should be tied low
and TCK, TDI, and TMS should be pulled through a resistor to 3.3V. TDO should be left unconnected.
4. On future 18M device CS0 will be removed, B2 will be be used for address expansion.
6.42
7