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IDT71V65803S150BQI PDF预览

IDT71V65803S150BQI

更新时间： 2024-11-07 22:38:31
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路静态存储器
页数 文件大小 规格书
26页 497K
描述
256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs

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中文翻译

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IDT71V65803S150BQI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：BGA
包装说明：TBGA, BGA165,11X15,40针数：165
Reach Compliance Code：not_compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.11
Is Samacsys：N最长访问时间：3.8 ns
I/O 类型：COMMONJESD-30 代码：R-PBGA-B165
JESD-609代码：e0长度：15 mm
内存密度：9437184 bit内存集成电路类型：ZBT SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：165
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：225
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.2 mm最大待机电流：0.06 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.345 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn63Pb37)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：20
宽度：13 mmBase Number Matches：1

IDT71V65803S150BQI 数据手册

 浏览型号IDT71V65803S150BQI的Datasheet PDF文件第2页浏览型号IDT71V65803S150BQI的Datasheet PDF文件第3页浏览型号IDT71V65803S150BQI的Datasheet PDF文件第4页浏览型号IDT71V65803S150BQI的Datasheet PDF文件第5页浏览型号IDT71V65803S150BQI的Datasheet PDF文件第6页浏览型号IDT71V65803S150BQI的Datasheet PDF文件第7页 
256K x 36, 512K x 18  
3.3V Synchronous ZBT™ SRAMs  
ZBT™Feature  
IDT71V65603  
IDT71V65803  
3.3V I/O, Burst Counter  
PipelinedOutputs  
Features  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.  
TheIDT71V65603/5803containdataI/O,addressandcontrolsignal  
registers.Outputenableistheonlyasynchronoussignalandcanbeused  
todisabletheoutputsatanygiventime.  
◆
256K x 36, 512K x 18 memory configurations  
◆
Supports high performance system speed - 150MHz  
(3.8ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read cycles  
◆
◆
Internally synchronized output buffer enable eliminates the  
AClockEnable(CEN)pinallowsoperationoftheIDT71V65603/5803to  
besuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen  
(CEN)ishighandtheinternaldeviceregisterswillholdtheirpreviousvalues.  
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser  
todeselectthedevicewhendesired.Ifanyoneofthesethreearenotasserted  
whenADV/LDislow,nonewmemoryoperationcanbeinitiated.However,  
anypendingdatatransfers(readsorwrites)willbecompleted.Thedatabus  
willtri-statetwocyclesafterchipisdeselectedorawriteisinitiated.  
TheIDT71V65603/5803haveanon-chipburstcounter.Intheburst  
mode,theIDT71V65603/5803canprovidefourcyclesofdataforasingle  
address presented to the SRAM. The order of the burst sequence is  
defined by the LBO input pin. The LBO pin selects between linear and  
interleaved burst sequence. The ADV/LD signal is used to load a new  
externaladdress(ADV/LD=LOW) orincrementtheinternalburstcounter  
(ADV/LD = HIGH).  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%)  
3.3V I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array(fBGA).  
◆
◆
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◆
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Description  
The IDT71V65603/5803 are 3.3V high-speed 9,437,184-bit  
(9Megabit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbus  
cycleswhenturningthebusaroundbetweenreadsandwrites,orwritesand  
The IDT71V65603/5803 SRAM utilize IDT's latest high-performance  
CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm100-  
pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray(BGA)and  
165 fine pitch ball grid array (fBGA) .  
TM  
reads.Thus,theyhavebeengiventhenameZBT ,orZeroBusTurnaround.  
PinDescriptionSummary  
0
18  
A -A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
1
2
2
CE , CE , CE  
Output Enable  
OE  
R/W  
CEN  
Read/Write Signal  
Clock Enable  
Individual Byte Write Selects  
Clock  
1
2
3
4
BW , BW , BW , BW  
CLK  
ADV/LD  
LBO  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Static  
ZZ  
Asynchronous  
Synchronous  
Static  
0
31  
P1  
P4  
I/O -I/O , I/O -I/O  
Data Input / Output  
Core Power, I/O Power  
Ground  
DD DDQ  
V , V  
Supply  
Supply  
SS  
V
Static  
5304 tbl 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.  
DECEMBER 2002  
1
©2002IntegratedDeviceTechnology,Inc.  
DSC-5304/05  
1234567...26

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与IDT71V65803S150BQI相关器件

型号 品牌 获取价格 描述 数据表
IDT71V65803S150BQI8 IDT

获取价格

 		ZBT SRAM, 512KX18, 3.8ns, CMOS, PBGA165, 13 X 15 MM, FINE PITCH, BGA-165
IDT71V65803S150PF IDT

获取价格

 		256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs
IDT71V65803S150PFG IDT

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 		ZBT SRAM, 512KX18, 3.8ns, CMOS, PQFP100, PLASTIC, MO-136, TQFP-100
IDT71V65803S150PFG8 IDT

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 		ZBT SRAM, 512KX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
IDT71V65803S150PFGI IDT

获取价格

 		ZBT SRAM, 512KX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136, TQFP
IDT71V65803S150PFGI8 IDT

获取价格

 		ZBT SRAM, 512KX18, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, POWER, PLASTIC, TQFP-
IDT71V65803S150PFI IDT

获取价格

 		256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs
IDT71V65803Z IDT

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 		3.3V Synchronous ZBT SRAMs
IDT71V65803Z100BGG IDT

获取价格

 		ZBT SRAM, 512KX18, 3.8ns, CMOS, PBGA119, 14.0 X 22.0 MM, ROHS COMPLIANT, BGA-119
IDT71V65803Z100BGGI IDT

获取价格

 		ZBT SRAM, 512KX18, 3.8ns, CMOS, PBGA119, 14.0 X 22.0 MM, ROHS COMPLIANT, BGA-119

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