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IDT71V65803S100PFI8 PDF预览

IDT71V65803S100PFI8

更新时间： 2024-11-08 14:38:03
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
26页 397K
描述
ZBT SRAM, 512KX18, 5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100

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IDT71V65803S100PFI8 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：QFP包装说明：14 X 20 MM, PLASTIC, TQFP-100
针数：100Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.11Is Samacsys：N
最长访问时间：5 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：100 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
长度：20 mm内存密度：9437184 bit
内存集成电路类型：ZBT SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：100字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：240电源：3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.06 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.27 mA
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20宽度：14 mm
Base Number Matches：1

IDT71V65803S100PFI8 数据手册

 浏览型号IDT71V65803S100PFI8的Datasheet PDF文件第2页浏览型号IDT71V65803S100PFI8的Datasheet PDF文件第3页浏览型号IDT71V65803S100PFI8的Datasheet PDF文件第4页浏览型号IDT71V65803S100PFI8的Datasheet PDF文件第5页浏览型号IDT71V65803S100PFI8的Datasheet PDF文件第6页浏览型号IDT71V65803S100PFI8的Datasheet PDF文件第7页 
256K x 36, 512K x 18  
3.3V Synchronous ZBT™ SRAMs  
ZBT™ Feature  
IDT71V65603/Z  
IDT71V65803/Z  
3.3V I/O, Burst Counter  
Pipelined Outputs  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.  
TheIDT71V65603/5803containdataI/O,addressandcontrolsignal  
registers.Outputenableistheonlyasynchronoussignalandcanbeused  
todisabletheoutputsatanygiventime.  
A Clock Enable (CEN) pin allows operation of the IDT71V65603/5803  
tobesuspendedaslongasnecessary.Allsynchronousinputsareignored  
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious  
values.  
Therearethreechipenablepins(CE1, CE2, CE2)thatallowtheuser  
to deselect the device when desired. If any one of these three are not  
asserted when ADV/LD is low, no new memory operation can be  
initiated. However, any pending data transfers (reads or writes) will be  
completed. The data bus will tri-state two cycles after chip is deselected  
or a write is initiated.  
TheIDT71V65603/5803haveanon-chipburstcounter.Intheburst  
mode, the IDT71V65603/5803 can provide four cycles of data for a  
single address presented to the SRAM. The order of the burst  
sequence is defined by the LBO input pin. The LBO pin selects  
between linear and interleaved burst sequence. The ADV/LD signal is  
used to load a new external address (ADV/LD = LOW) or increment  
the internal burst counter (ADV/LD = HIGH).  
Features  
◆
256K x 36, 512K x 18 memory configurations  
◆
Supports high performance system speed - 150MHz  
(3.8ns Clock-to-Data Access)  
◆
ZBTTM Feature - No dead cycles between write and read cycles  
◆
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control signal  
◆
◆
registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%)  
3.3V I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Packaged in a JEDEC standard 100-pin plastic thin quad  
◆
◆
◆
◆
◆
◆
◆
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array(fBGA).  
Description  
The IDT71V65603/5803 are 3.3V high-speed 9,437,184-bit  
(9Megabit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbus  
cycleswhenturningthebusaroundbetweenreadsandwrites, orwritesand  
reads. Thus, they have been given the name ZBTTM, or Zero Bus Turn-  
around.  
The IDT71V65603/5803 SRAM utilize IDT's latest high-performance  
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm  
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array  
(BGA) and 165 fine pitch ball grid array (fBGA) .  
Pin Description Summary  
A
0-A18  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE1  
, CE  
2
, CE  
2
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW  
1
, BW  
2
, BW  
3
, BW  
4
CLK  
ADV/LD  
LBO  
Advance burst address / Load new address  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Static  
ZZ  
Asynchronous  
Synchronous  
Static  
I/O  
0
-I/O31, I/OP1-I/OP4  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
V
DD, VDDQ  
SS  
Supply  
Supply  
Static  
5304 tbl 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.  
OCTOBER 2008  
1
©2008 Integrated Device Technology, Inc.  
DSC-5304/08  
1234567...26

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与IDT71V65803S100PFI8相关器件

型号 品牌 获取价格 描述 数据表
IDT71V65803S133BG IDT

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 		256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs
IDT71V65803S133BG8 IDT

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 		ZBT SRAM, 512KX18, 4.2ns, CMOS, PBGA119, BGA-119
IDT71V65803S133BGG IDT

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 		ZBT SRAM, 512KX18, 4.2ns, CMOS, PBGA119, MS-028AA, BGA-119
IDT71V65803S133BGG8 IDT

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 		ZBT SRAM, 512KX18, 4.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MO-028AA, BGA-119
IDT71V65803S133BGGI IDT

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 		暂无描述
IDT71V65803S133BGGI8 IDT

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 		ZBT SRAM, 512KX18, 4.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MO-028AA, BGA-119
IDT71V65803S133BGI IDT

获取价格

 		256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs
IDT71V65803S133BQ IDT

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 		256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs
IDT71V65803S133BQG IDT

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 		ZBT SRAM, 512KX18, 4.2ns, CMOS, PBGA165, FBGA-165
IDT71V65803S133BQGI IDT

获取价格

 		ZBT SRAM, 512KX18, 4.2ns, CMOS, PBGA165, FBGA-165

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