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IDT71V65802S166BG PDF预览

IDT71V65802S166BG

更新时间: 2024-09-20 09:42:07
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
23页 305K
描述
ZBT SRAM, 512KX18, 3.5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119

IDT71V65802S166BG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:14 X 22 MM, PLASTIC, BGA-119针数:119
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.72
最长访问时间:3.5 nsJESD-30 代码:R-PBGA-B119
JESD-609代码:e3长度:22 mm
内存密度:9437184 bit内存集成电路类型:ZBT SRAM
内存宽度:18湿度敏感等级:1
功能数量:1端子数量:119
字数:524288 words字数代码:512000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512KX18
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:RECTANGULAR封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:3.5 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:14 mm

IDT71V65802S166BG 数据手册

 浏览型号IDT71V65802S166BG的Datasheet PDF文件第2页浏览型号IDT71V65802S166BG的Datasheet PDF文件第3页浏览型号IDT71V65802S166BG的Datasheet PDF文件第4页浏览型号IDT71V65802S166BG的Datasheet PDF文件第5页浏览型号IDT71V65802S166BG的Datasheet PDF文件第6页浏览型号IDT71V65802S166BG的Datasheet PDF文件第7页 
256K x 36, 512K x 18  
Preliminary  
IDT71V65602  
IDT71V65802  
3.3VSynchronousZBTSRAMs  
2.5V I/O, Burst Counter  
PipelinedOutputs  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.  
TheIDT71V65602/5802containdataI/O,addressandcontrolsignal  
registers.Outputenableistheonlyasynchronoussignalandcanbeused  
todisabletheoutputsatanygiventime.  
AClockEnable(CEN)pinallowsoperationoftheIDT71V65602/5802  
to be suspended as long as necessary. All synchronous inputs are  
ignoredwhen(CEN)ishighandtheinternaldeviceregisterswillholdtheir  
previous values.  
Features  
256K x 36, 512K x 18 memory configurations  
Supports high performance system speed - 166MHz(3.5ns  
Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read cycles  
Internally synchronized output buffer enable eliminates  
the need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
There are three chip enable pins (CE1, CE2, CE2) that allow the  
user to deselect the device when desired. If any one of these three are  
not asserted when ADV/LD is low, no new memory operation can be  
initiated. However, any pending data transfers (reads or writes) will be  
completed.Thedatabuswilltri-statetwocyclesafterchipisdeselectedor  
awriteisinitiated.  
TheIDT71V65602/5802haveanon-chipburstcounter.Intheburst  
mode,theIDT71V65602/5802canprovidefourcyclesofdataforasingle  
address presented to the SRAM. The order of the burst sequence is  
defined by the LBO input pin. The LBO pin selects between linear and  
interleaved burst sequence. The ADV/LD signal is used to load a new  
externaladdress(ADV/LD=LOW) orincrementtheinternalburstcounter  
(ADV/LD = HIGH).  
The IDT71V65602/5802 SRAM utilize IDT's latest high-performance  
CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm100-  
leadthinplasticquadflatpack(TQFP)aswellasa119-leadballgridarray(BGA).  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%)  
2.5V I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Packaged in a JEDEC standard 100-lead plastic thin quad  
Description  
The IDT71V65602/5802 are 3.3V high-speed 9,437,184-bit  
(9Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead  
bus cycles when turning the bus around between reads and writes, or  
writes andreads.Thus,theyhavebeengiventhenameZBT ,orZero  
Bus Turnaround.  
TM  
PinDescriptionSummary  
A
0
-A18  
Addres s Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Output  
Input  
I/O  
Synchronous  
Synchronous  
As ynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE  
1
, CE  
2
,
CE  
2
Output Enable  
OE  
R/  
W
Re ad/Write Signal  
Clock Enable  
CEN  
BW  
Individual Byte Write Se le cts  
Clock  
1
,
BW  
2
,
BW  
3
,
BW  
4
CLK  
ADV/LD  
LBO  
TMS  
TDI  
Advance burst addres s / Load new addre ss  
Line ar / Inte rle ave d Burs t Orde r  
Te st Mode Se lect  
Te st Data Input  
Synchronous  
Static  
N/A  
N/A  
TCK  
TDO  
ZZ  
Te s t Clo c k  
N/A  
Te s t Data O utp ut  
Slee p Mode  
N/A  
As ynchronous  
Synchronous  
Static  
I/O  
0
-I/O31, I/OP1-I/OP4  
Data Input / Outp ut  
Core Powe r, I/O Powe r  
Ground  
VDD, VDDQ  
Supply  
Supply  
V
SS  
Static  
5303 tbl 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.  
DECEMBER 1999  
1
©1999IntegratedDeviceTechnology,Inc.  
DSC-5303/00  

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256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs