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IDT71V424YFS15PH PDF预览

IDT71V424YFS15PH

更新时间: 2024-11-07 19:47:51
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
9页 85K
描述
Standard SRAM, 512KX8, 15ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44

IDT71V424YFS15PH 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSOP2
包装说明:0.400 INCH, TSOP2-44针数:44
Reach Compliance Code:not_compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.31
最长访问时间:15 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G44JESD-609代码:e0
长度:18.41 mm内存密度:4194304 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:44字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP44,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.02 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.16 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:10.16 mm
Base Number Matches:1

IDT71V424YFS15PH 数据手册

 浏览型号IDT71V424YFS15PH的Datasheet PDF文件第2页浏览型号IDT71V424YFS15PH的Datasheet PDF文件第3页浏览型号IDT71V424YFS15PH的Datasheet PDF文件第4页浏览型号IDT71V424YFS15PH的Datasheet PDF文件第5页浏览型号IDT71V424YFS15PH的Datasheet PDF文件第6页浏览型号IDT71V424YFS15PH的Datasheet PDF文件第7页 
IDT71V424S  
IDT71V424L  
3.3V CMOS Static RAM  
4 Meg (512K x 8-Bit)  
Features  
Description  
512K x 8 advanced high-speed CMOS Static RAM  
JEDEC Center Power / GND pinout for reduced noise  
Equal access and cycle times  
TheIDT71V424isa4,194,304-bithigh-speedStaticRAMorganized  
as512Kx8.ItisfabricatedusingIDT’shigh-perfomance,high-reliability  
CMOStechnology.Thisstate-of-the-arttechnology,combinedwithinno-  
vativecircuitdesigntechniques,providesacost-effectivesolutionforhigh-  
speedmemoryneeds.  
— CommercialandIndustrial:10/12/15ns  
Single 3.3V power supply  
One Chip Select plus one Output Enable pin  
Bidirectional data inputs and outputs directly  
TTL-compatible  
Low power consumption via chip deselect  
Available in 36-pin, 400 mil plastic SOJ package and  
44-pin, 400 mil TSOP.  
TheIDT71V424hasanoutputenablepinwhichoperatesasfastas  
5ns,withaddressaccesstimesasfastas10ns.Allbidirectionalinputsand  
outputs of the IDT71V424 are TTL-compatible and operation is from a  
single3.3Vsupply.Fullystaticasynchronouscircuitryisused,requiring  
noclocks orrefreshforoperation.  
TheIDT71V424ispackagedina36-pin,400milPlasticSOJand44-  
pin,400milTSOP.  
FunctionalBlockDiagram  
0
A
4,194,304-BIT  
MEMORY ARRAY  
ADDRESS  
DECODER  
A
18  
8
8
I/O - I/O  
0 7  
I/O CONTROL  
8
WE  
OE  
CS  
CONTROL  
LOGIC  
3622 drw 01  
NOVEMBER 2002  
1
©2002IntegratedDeviceTechnology,Inc.  
DSC-3622/04  

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