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IDT71V424YS12PHG PDF预览

IDT71V424YS12PHG

更新时间: 2024-11-08 10:31:51
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器光电二极管
页数 文件大小 规格书
9页 479K
描述
Standard SRAM, 512KX8, 12ns, CMOS, PDSO44, 0.400 INCH, ROHS COMPLIANT, TSOP2-44

IDT71V424YS12PHG 数据手册

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IDT71V424YS  
IDT71V424YL  
3.3V CMOS Static RAM  
4 Meg (512K x 8-Bit)  
Features  
Description  
512K x 8 advanced high-speed CMOS Static RAM  
JEDEC Center Power / GND pinout for reduced noise  
Equal access and cycle times  
TheIDT71V424isa4,194,304-bithigh-speedStaticRAMorganized  
as512Kx8.ItisfabricatedusingIDT’shigh-perfomance,high-reliability  
CMOStechnology.Thisstate-of-the-arttechnology,combinedwithinno-  
vativecircuitdesigntechniques,providesacost-effectivesolutionforhigh-  
speedmemoryneeds.  
— CommercialandIndustrial:10/12/15ns  
Single 3.3V power supply  
One Chip Select plus one Output Enable pin  
Bidirectional data inputs and outputs directly  
TTL-compatible  
Low power consumption via chip deselect  
Available in 36-pin, 400 mil plastic SOJ package and  
44-pin, 400 mil TSOP.  
TheIDT71V424hasanoutputenablepinwhichoperatesasfastas  
5ns,withaddressaccesstimesasfastas10ns.Allbidirectionalinputsand  
outputs of the IDT71V424 are TTL-compatible and operation is from a  
single3.3Vsupply.Fullystaticasynchronouscircuitryisused,requiring  
noclocks orrefreshforoperation.  
TheIDT71V424ispackagedina36-pin,400milPlasticSOJand44-  
pin,400milTSOP.  
FunctionalBlockDiagram  
A
0
4,194,304-BIT  
MEMORY ARRAY  
ADDRESS  
DECODER  
A18  
8
8
I/O0 - I/O7  
I/O CONTROL  
8
WE  
OE  
CS  
CONTROL  
LOGIC  
6468 drw 01  
JULY 2004  
1
©2004IntegratedDeviceTechnology,Inc.  
DSC-6468/00  

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