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IDT71V428L10Y PDF预览

IDT71V428L10Y

更新时间: 2024-11-07 21:14:27
品牌 Logo 应用领域
艾迪悌 - IDT 输入元件静态存储器光电二极管输出元件内存集成电路
页数 文件大小 规格书
9页 81K
描述
Standard SRAM, 1MX4, 10ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32

IDT71V428L10Y 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOJ包装说明:0.400 INCH, PLASTIC, SOJ-32
针数:32Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.57最长访问时间:10 ns
其他特性:TTL-COMPATIBLE INPUTS & OUTPUTSI/O 类型:COMMON
JESD-30 代码:R-PDSO-J32JESD-609代码:e0
长度:20.96 mm内存密度:4194304 bit
内存集成电路类型:STANDARD SRAM内存宽度:4
湿度敏感等级:3功能数量:1
端子数量:32字数:1048576 words
字数代码:1000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:1MX4输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ32,.44封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified座面最大高度:3.76 mm
最大待机电流:0.01 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.14 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:10.16 mm
Base Number Matches:1

IDT71V428L10Y 数据手册

 浏览型号IDT71V428L10Y的Datasheet PDF文件第2页浏览型号IDT71V428L10Y的Datasheet PDF文件第3页浏览型号IDT71V428L10Y的Datasheet PDF文件第4页浏览型号IDT71V428L10Y的Datasheet PDF文件第5页浏览型号IDT71V428L10Y的Datasheet PDF文件第6页浏览型号IDT71V428L10Y的Datasheet PDF文件第7页 
3.3V CMOS Static RAM  
4 Meg (1M x 4-Bit)  
IDT71V428S  
IDT71V428L  
Features  
Description  
1M x 4 advanced high-speed CMOS Static RAM  
JEDEC Center Power / GND pinout for reduced noise  
Equal access and cycle times  
The IDT71V428 is a 4,194,304-bit high-speed Static RAM orga-  
nized as 1M x 4. It is fabricated using IDTs high-perfomance, high-  
reliability CMOS technology. This state-of-the-art technology, com-  
bined with innovative circuit design techniques, provides a cost-  
effective solution for high-speed memory needs.  
— Commercial and Industrial: 10/12/15ns  
Single 3.3V power supply  
One Chip Select plus one Output Enable pin  
Bidirectional data inputs and outputs directly  
LVTTL-compatible  
TheIDT71V428has anoutputenablepinwhichoperates as fastas  
5ns, withaddress access times as fastas 10ns. Allbidirectionalinputs  
andoutputs ofthe IDT71V428are LVTTL-compatible andoperationis  
from a single 3.3V supply. Fully static asynchronous circuitry is used,  
requiringnoclocks orrefreshforoperation.  
Low power consumption via chip deselect  
Available in 32-pin, 400 mil plastic SOJ package.  
The IDT71V428 is packaged in a 32-pin, 400 mil Plastic SOJ.  
Functional Block Diagram  
A0  
4,194,304-BIT  
MEMORY ARRAY  
ADDRESS  
DECODER  
A19  
4
4
I/O0 I/O3  
I/O CONTROL  
4
WE  
OE  
CS  
CONTROL  
LOGIC  
3623 drw 01  
SEPTEMBER 1999  
1
©1999 Integrated Device Technology, Inc.  
DSC-3623/3  

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