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IDT71V3579S85BQGI PDF预览

IDT71V3579S85BQGI

更新时间： 2024-10-27 23:10:11
品牌 Logo 应用领域
艾迪悌 - IDT 计数器存储内存集成电路静态存储器
页数 文件大小 规格书
22页 522K
描述
128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect

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IDT71V3579S85BQGI 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：FBGA-165
针数：165Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.74Is Samacsys：N
最长访问时间：8.5 ns其他特性：FLOW-THROUGH ARCHITECTURE
JESD-30 代码：R-PBGA-B165JESD-609代码：e1
长度：15 mm内存密度：4718592 bit
内存集成电路类型：CACHE SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：165字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256KX18封装主体材料：PLASTIC/EPOXY
封装代码：TBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN SILVER COPPER
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：13 mmBase Number Matches：1

IDT71V3579S85BQGI 数据手册

 浏览型号IDT71V3579S85BQGI的Datasheet PDF文件第1页浏览型号IDT71V3579S85BQGI的Datasheet PDF文件第3页浏览型号IDT71V3579S85BQGI的Datasheet PDF文件第4页浏览型号IDT71V3579S85BQGI的Datasheet PDF文件第5页浏览型号IDT71V3579S85BQGI的Datasheet PDF文件第6页浏览型号IDT71V3579S85BQGI的Datasheet PDF文件第7页 
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
PinDefinitions(1)  
Symbol  
Pin Function  
I/O  
Active  
Description  
A0-A17  
Address Inputs  
I
N/A  
Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of CLK  
and ADSC Low or ADSP Low and CE Low.  
Address Status  
(Cache Controller)  
I
I
I
LOW  
LOW  
LOW  
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the  
address registers with new addresses.  
ADSC  
ADSP  
ADV  
Address Status  
(Processor)  
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the address  
registers with new addresses. ADSP is gated by CE.  
Burst Address  
Advance  
Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst counter,  
controlling burst access after the initial address is loaded. When the input is HIGHthe burst counter is not  
incremented; that is, there is no address advance.  
Byte Write Enable  
I
I
LOW  
LOW  
Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising edge of CLK  
then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are  
blocked and only GW can initiate a write cycle.  
BWE  
Individual Byte  
Write Enables  
Synchronous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any active byte  
write causes all outputs to be disabled.  
BW1-BW4  
Chip Enable  
Clock  
I
I
I
I
I
LOW  
N/A  
Synchronous chip enable. CE is used with CS0 and CS1 to enable the IDT71V3577/79. CE also gates ADSP.  
This is the clock input. All timing references for the device are made with respect to this input.  
Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable the chip.  
Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the chip.  
CE  
CLK  
CS0  
CS1  
GW  
Chip Select 0  
Chip Select 1  
HIGH  
LOW  
LOW  
Global Write  
Enable  
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of  
CLK. GW supersedes individual byte write enables.  
I/O0-I/O31  
I/OP1-I/OP4  
Data Input/Output  
I/O  
I
N/A  
Synchronous data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of  
CLK. The data outputpath is flow-through (no output register).  
Linear Burst Order  
LOW  
Asynchronous burst order selection input. When LBO is HIGH, the inter-leaved burst sequence is selected.  
When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not change state  
while the device is operating.  
LBO  
Output Enable  
I
LOW  
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the chip  
is also selected. When OE is HIGH the I/O pins are in a high-impedance state.  
OE  
TMS  
TDI  
Test ModeSelect  
Test Data Input  
I
I
N/A  
N/A  
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.  
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an  
internal pullup.  
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,  
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.  
TCK  
TDO  
Test Clock  
I
N/A  
N/A  
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the  
TAP controller.  
Test DataOutput  
O
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset  
occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can  
be left floating. This pin has an internal pullup. Only available in BGA package.  
JTAG Reset  
(Optional)  
I
I
LOW  
TRST  
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V3577/79 to  
HIGH its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal pull  
down.  
ZZ  
Sleep Mode  
VDD  
VDDQ  
VSS  
Power Supply  
Power Supply  
Ground  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
3.3V core power supply.  
3.3V I/O Supply.  
Ground.  
NC  
No Connect  
NC pins are not electrically connected to the device.  
5280 tbl 02  
NOTE:  
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.  
6.422  
1234567...22

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