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IDT71V3579S85BQGI PDF预览

IDT71V3579S85BQGI

更新时间: 2024-10-27 23:10:11
品牌 Logo 应用领域
艾迪悌 - IDT 计数器存储内存集成电路静态存储器
页数 文件大小 规格书
22页 522K
描述
128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect

IDT71V3579S85BQGI 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:FBGA-165
针数:165Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.74Is Samacsys:N
最长访问时间:8.5 ns其他特性:FLOW-THROUGH ARCHITECTURE
JESD-30 代码:R-PBGA-B165JESD-609代码:e1
长度:15 mm内存密度:4718592 bit
内存集成电路类型:CACHE SRAM内存宽度:18
湿度敏感等级:3功能数量:1
端子数量:165字数:262144 words
字数代码:256000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:256KX18封装主体材料:PLASTIC/EPOXY
封装代码:TBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN SILVER COPPER
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:13 mmBase Number Matches:1

IDT71V3579S85BQGI 数据手册

 浏览型号IDT71V3579S85BQGI的Datasheet PDF文件第4页浏览型号IDT71V3579S85BQGI的Datasheet PDF文件第5页浏览型号IDT71V3579S85BQGI的Datasheet PDF文件第6页浏览型号IDT71V3579S85BQGI的Datasheet PDF文件第8页浏览型号IDT71V3579S85BQGI的Datasheet PDF文件第9页浏览型号IDT71V3579S85BQGI的Datasheet PDF文件第10页 
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with  
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect  
Commercial and Industrial Temperature Ranges  
Pin Configuration – 128K x 36, 119 BGA  
1
2
3
4
5
6
7
DDQ  
6
4
8
16  
DDQ  
V
V
A
A
A
A
A
A
A
A
B
C
D
E
F
ADSP  
ADSC  
3
2
9
1
CS  
NC  
NC  
CS  
NC  
NC  
0
7
A
DD  
V
12  
15  
A
A
16  
I/O  
P3  
I/O  
SS  
SS  
SS  
SS  
SS  
SS  
P2  
I/O  
15  
I/O  
V
V
V
NC  
CE  
V
V
V
17  
I/O  
18  
I/O  
13  
I/O  
14  
I/O  
DDQ  
19  
I/O  
12  
I/O  
DDQ  
V
V
V
V
V
V
OE  
20  
I/O  
21  
I/O  
3
2
BW  
11  
I/O  
10  
I/O  
G
H
J
BW  
ADV  
GW  
22  
I/O  
23  
I/O  
SS  
SS  
9
I/O  
8
I/O  
V
V
DDQ  
24  
DD  
DD  
V
DD  
V
DDQ  
V
NC  
NC  
26  
I/O  
SS  
SS  
6
I/O  
7
I/O  
I/O  
V
CLK  
NC  
V
K
L
25  
I/O  
27  
I/O  
4
1
BW  
4
I/O  
5
I/O  
BW  
DDQ  
29  
28  
I/O  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
3
I/O  
DDQ  
V
V
V
V
V
V
V
M
N
P
R
T
BWE  
30  
I/O  
1
0
2
I/O  
1
I/O  
I/O  
A
31  
P4  
I/O  
0
I/O  
P1  
I/O  
I/O  
NC  
A
5
A
DD  
V
13  
A
NC  
LBO  
(3)  
10  
11  
A
14  
NC  
NC  
A
A
NC  
ZZ  
(2)  
(2)  
(2)  
(2)  
(2,4)  
NC/TDO  
DDQ  
V
DDQ  
V
NC/TMS  
NC/TDI  
NC/TCK  
NC/TRST  
U
5280 drw 02c  
Top View  
Pin Configuration – 256K x 18, 119 BGA  
1
2
3
4
5
6
7
DDQ  
6
4
8
16  
A
DDQ  
V
A
B
C
D
E
F
V
A
A
A
A
A
A
ADSP  
ADSC  
3
2
9
CS1  
NC  
NC  
CS0  
NC  
NC  
NC  
7
A
DD  
V
13  
A
17  
A
8
I/O  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
7
I/O  
NC  
V
V
V
NC  
CE  
V
V
V
V
V
9
I/O  
6
I/O  
NC  
DDQ  
NC  
5
I/O  
DDQ  
V
V
NC  
OE  
10  
I/O  
4
I/O  
BW2  
ADV  
GW  
NC  
NC  
G
H
J
11  
I/O  
SS  
V
3
I/O  
NC  
NC  
DDQ  
V
DD  
V
DD  
V
DD  
V
DDQ  
V
NC  
NC  
SS  
12  
I/O  
SS  
V
2
I/O  
K
L
NC  
CLK  
NC  
V
NC  
SS  
V
13  
I/O  
1
I/O  
BW1  
NC  
NC  
DDQ  
14  
SS  
V
SS  
V
DDQ  
V
M
N
P
R
T
V
I/O  
NC  
BWE  
15  
I/O  
SS  
V
1
A
SS  
V
0
I/O  
NC  
NC  
P2  
SS  
V
0
A
SS  
V
P1  
I/O  
NC  
NC  
NC  
DDQ  
I/O  
NC  
5
DD  
V
SS  
V
12  
A
A
NC  
LBO  
ZZ(3)  
10  
A
15  
A
14  
A
11  
A
NC  
NC/TDO(2)  
DDQ  
V
NC/TMS(2) NC/TDI(2) NC/TCK(2)  
NC/TRST(2,4)  
U
V
5280 drw 02d  
,
Top View  
NOTES:  
1. R5 does not have to be directly connected to VSS as long as the input voltage is < VIL.  
2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.  
3. T7 can be left unconnected and the device will always remain in active mode.  
4. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.  
6.42  
7

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